Issued Patents All Time
Showing 626–650 of 719 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7405994 | Dual port cell structure | — | 2008-07-29 |
| 7403413 | Multiple port resistive memory cell | — | 2008-07-22 |
| 7394714 | Circuit implementation of a dynamic power supply for SRAM core array | Wesley Lin, Fang-Shi Jordan Lai, Chia-Fu Lee | 2008-07-01 |
| 7394155 | Top and sidewall bridged interconnect structure and method | — | 2008-07-01 |
| 7365432 | Memory cell structure | — | 2008-04-29 |
| 7364961 | SRAM cell design for soft error rate immunity | — | 2008-04-29 |
| 7355233 | Apparatus and method for multiple-gate semiconductor device with angled sidewalls | — | 2008-04-08 |
| 7354833 | Method for improving threshold voltage stability of a MOS device | — | 2008-04-08 |
| 7316979 | Method and apparatus for providing an integrated active region on silicon-on-insulator devices | — | 2008-01-08 |
| 7307871 | SRAM cell design with high resistor CMOS gate structure for soft error rate improvement | — | 2007-12-11 |
| 7292467 | Magnetic random access memory device | — | 2007-11-06 |
| 7286429 | High speed sensing amplifier for an MRAM cell | Denny Tang | 2007-10-23 |
| 7271451 | Memory cell structure | — | 2007-09-18 |
| 7269056 | Power grid design for split-word line style memory cell | — | 2007-09-11 |
| 7257017 | SRAM cell for soft-error rate reduction and cell stability improvement | — | 2007-08-14 |
| 7250657 | Layout structure for memory arrays with SOI devices | — | 2007-07-31 |
| 7236391 | Magnetic random access memory device | — | 2007-06-26 |
| 7233032 | SRAM device having high aspect ratio cell boundary | — | 2007-06-19 |
| 7203112 | Multiple stage method and system for sensing outputs from memory cells | — | 2007-04-10 |
| 7202566 | Crossed power strapped layout for full CMOS circuit design | — | 2007-04-10 |
| 7193292 | Fuse structure with charge protection circuit | — | 2007-03-20 |
| 7187036 | Connection structure for SOI devices | — | 2007-03-06 |
| 7176125 | Method of forming a static random access memory with a buried local interconnect | — | 2007-02-13 |
| 7146599 | Method for using asymmetric OPC structures on line ends of semiconductor pattern layers | — | 2006-12-05 |
| 7119023 | Process integration of SOI FETs with active layer spacer | — | 2006-10-10 |