Issued Patents All Time
Showing 76–99 of 99 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9373695 | Method for improving selectivity of epi process | Kuan-Yu Chen, Hsien-Hsin Lin, Chun-Feng Nieh, Chien-Chang Su, Tsz-Mei Kwok | 2016-06-21 |
| 9362360 | Modulating germanium percentage in MOS devices | Tsz-Mei Kwok, Kun-Mu Li, Chii-Horng Li, Tze-Liang Lee | 2016-06-07 |
| 9356150 | Method for incorporating impurity element in EPI silicon process | Chien-Chang Su, Hsien-Hsin Lin, Tsz-Mei Kwok, Kuan-Yu Chen, Yi-Fang Pai | 2016-05-31 |
| 9337337 | MOS device having source and drain regions with embedded germanium-containing diffusion barrier | Tsz-Mei Kwok, Kun-Mu Li, Chii-Horng Li, Tze-Liang Lee | 2016-05-10 |
| 9293537 | High performance strained source-drain structure and method of fabricating the same | Ming-Huan Tsai, Hsien-Hsin Lin, Chun-Fai Cheng, Wei-Han Fan | 2016-03-22 |
| 9287398 | Transistor strain-inducing scheme | Tsz-Mei Kwok, Kun-Mu Li, Chii-Horng Li, Tze-Liang Lee | 2016-03-15 |
| 9209175 | MOS devices having epitaxy regions with reduced facets | Tsz-Mei Kwok, Kun-Mu Li, Tze-Liang Lee, Chii-Horng Li | 2015-12-08 |
| 9117905 | Method for incorporating impurity element in EPI silicon process | Chien-Chang Su, Hsien-Hsin Lin, Tsz-Mei Kwok, Kuan-Yu Chen, Yi-Fang Pai | 2015-08-25 |
| 9012964 | Modulating germanium percentage in MOS devices | Tsz-Mei Kwok, Kun-Mu Li, Chii-Horng Li, Tze-Liang Lee | 2015-04-21 |
| 8975144 | Controlling the shape of source/drain regions in FinFETs | Tsz-Mei Kwok, Chien-Chang Su, Kuan-Yu Chen, Hsien-Hsin Lin | 2015-03-10 |
| 8846461 | Silicon layer for stopping dislocation propagation | Hsien-Hsin Lin, Weng Chang, Chien-Chang Su, Kuan-Yu Chen, Ming-Hua Yu | 2014-09-30 |
| 8835982 | Method of manufacturing strained source/drain structures | Tsz-Mei Kwok, Kuan-Yu Chen, Hsien-Hsin Lin | 2014-09-16 |
| 8815713 | Reducing pattern loading effect in epitaxy | Tsz-Mei Kwok, Kuan-Yu Chen, Kun-Mu Li | 2014-08-26 |
| 8796788 | Semiconductor devices with strained source/drain structures | Tsz-Mei Kwok, Kuan-Yu Chen, Hsien-Hsin Lin | 2014-08-05 |
| 8765556 | Method of fabricating strained structure in semiconductor device | Yu-Rung Hsu, Chen-Hua Yu, Chao-Cheng Chen, Ming-Huan Tsai, Hsien-Hsin Lin | 2014-07-01 |
| 8709897 | High performance strained source-drain structure and method of fabricating the same | Ming-Huan Tsai, Hsien-Hsin Lin, Chun-Fai Cheng, Wei-Han Fan | 2014-04-29 |
| 8680625 | Facet-free semiconductor device | Wei-Han Fan, Yu-Hsien Lin, Yimin Huang, Ming-Huan Tsai, Chun-Fai Cheng | 2014-03-25 |
| 8558289 | Transistors having a composite strain structure, integrated circuits, and fabrication methods thereof | Chun-Fai Cheng, Kuan-Yu Chen, Hsien-Hsin Lin, Fung Ka Hing | 2013-10-15 |
| 8487354 | Method for improving selectivity of epi process | Kuan-Yu Chen, Hsien-Hsin Lin, Chun-Feng Nieh, Chien-Chang Su, Tsz-Mei Kwok | 2013-07-16 |
| 8368147 | Strained semiconductor device with recessed channel | Chun-Fai Cheng, Ka-Hing Fung, Han-Ting Tsai, Ming-Huan Tsai, Wei-Han Fan +4 more | 2013-02-05 |
| 8362575 | Controlling the shape of source/drain regions in FinFETs | Tsz-Mei Kwok, Chien-Chang Su, Kuan-Yu Chen, Hsien-Hsin Lin | 2013-01-29 |
| 8344447 | Silicon layer for stopping dislocation propagation | Hsien-Hsin Lin, Weng Chang, Chien-Chang Su, Kuan-Yu Chen, Ming-Hua Yu | 2013-01-01 |
| 8343872 | Method of forming strained structures with compound profiles in semiconductor devices | Hsien-Hsin Lin, Kuan-Yu Chen, Chien-Chang Su, Tsz-Mei Kwok, Yi-Fang Pai | 2013-01-01 |
| 8263451 | Epitaxy profile engineering for FinFETs | Chien-Chang Su, Tsz-Mei Kwok, Hsien-Hsin Lin, Yi-Fang Pai, Kuan-Yu Chen | 2012-09-11 |