Issued Patents All Time
Showing 26–50 of 99 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11437515 | Source and drain stressors with recessed top surfaces | Kun-Mu Li, Tsz-Mei Kwok, Chii-Horng Li, Tze-Liang Lee | 2022-09-06 |
| 11411098 | Devices with strained source/drain structures and method of forming the same | Tsz-Mei Kwok, Kuan-Yu Chen, Hsien-Hsin Lin | 2022-08-09 |
| 11411109 | MOS devices having epitaxy regions with reduced facets | Kun-Mu Li, Tze-Liang Lee, Chii-Horng Li, Tsz-Mei Kwok | 2022-08-09 |
| 11355620 | FinFET device and method of forming same | Chien-Wei Lee, Che-Yu Lin, Yee-Chia Yeo | 2022-06-07 |
| 11348840 | Semiconductor device and method | Wei-Min Liu, Yee-Chia Yeo | 2022-05-31 |
| 11296077 | Transistors with recessed silicon cap and method forming same | Yen-Ting Chen, Bo-Yu Lai, Chien-Wei Lee, Wei-Yang Lee, Feng-Cheng Yang +1 more | 2022-04-05 |
| 11271096 | Method for forming fin field effect transistor device structure | Chien-Wei Lee, Yen-Ru Lee, Yee-Chia Yeo | 2022-03-08 |
| 11217672 | Method of forming a source/drain | Chien-Wei Lee, Yen-Ru Lee | 2022-01-04 |
| 11211473 | Epitaxial fin structures having an epitaxial buffer region and an epitaxial capping region | Kun-Mu Li | 2021-12-28 |
| 11171209 | Semiconductor device and method of manufacture | Heng-Wen Ting, Kei-Wei Chen, Chii-Horng Li, Pei-Ren Jeng, Yen-Ru Lee +1 more | 2021-11-09 |
| 11164944 | Method of manufacturing a semiconductor device | Heng-Wen Ting | 2021-11-02 |
| 11158508 | Barrier layer above anti-punch through (APT) implant region to improve mobility of channel region of fin field effect transistor (finFET) device structure | Tsung-Yao Wen, Sheng-Chen Wang, Sai-Hooi Yeong, Ya-Yun Cheng | 2021-10-26 |
| 11145759 | Silicon germanium p-channel finFET stressor structure and method of making same | Liang Chen | 2021-10-12 |
| 11133416 | Methods of forming semiconductor devices having plural epitaxial layers | Yan-Ting Lin, Yen-Ru Lee | 2021-09-28 |
| 11107923 | Source/drain regions of FinFET devices and methods of forming same | Kun-Mu Li, Heng-Wen Ting, Yen-Ru Lee | 2021-08-31 |
| 11075120 | FinFET device and method | Kun-Mu Li, Heng-Wen Ting, Yen-Ru Lee, Chien-Wei Lee | 2021-07-27 |
| 11063152 | Semiconductor device and method | Chien-Wei Lee, Yen-Ru Lee, Jyun-Chih Lin, Tzu-Hsiang Hsu, Feng-Cheng Yang | 2021-07-13 |
| 10950725 | Epitaxial source/drain structure and method of forming same | Kun-Mu Li | 2021-03-16 |
| 10944005 | Interfacial layer between fin and source/drain region | Chih-Yun Chin, Chii-Horng Li, Chien-Wei Lee, Heng-Wen Ting, Roger Tai +5 more | 2021-03-09 |
| 10916656 | MOS devices having epitaxy regions with reduced facets | Kun-Mu Li, Tze-Liang Lee, Chii-Horng Li, Tsz-Mei Kwok | 2021-02-09 |
| 10879355 | Profile design for improved device performance | Kun-Mu Li, Yen-Ru Lee | 2020-12-29 |
| 10861971 | Doping profile for strained source/drain region | Tsz-Mei Kwok, Kun-Mu Li, Tze-Liang Lee, Chii-Horng Li | 2020-12-08 |
| 10797173 | MOS devices with non-uniform p-type impurity profile | Tsz-Mei Kwok, Kun-Mu Li, Tze-Liang Lee, Chii-Horng Li | 2020-10-06 |
| 10734520 | MOS devices having epitaxy regions with reduced facets | Kun-Mu Li, Tze-Liang Lee, Chii-Horng Li, Tsz-Mei Kwok | 2020-08-04 |
| 10727342 | Source and drain stressors with recessed top surfaces | Kun-Mu Li, Tsz-Mei Kwok, Chii-Horng Li, Tze-Liang Lee | 2020-07-28 |