Issued Patents All Time
Showing 51–75 of 94 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11610977 | Methods of forming nano-sheet-based devices having inner spacer structures with different widths | Jui-Chien Huang, Kuo-Cheng Chiang, Chih-Hao Wang, Shi Ning Ju | 2023-03-21 |
| 11581415 | Multi-layer channel structures and methods of fabricating the same in field-effect transistors | Kuo-Cheng Chiang, Shi Ning Ju, Chih-Hao Wang, Kuan-Lun Cheng | 2023-02-14 |
| 11552574 | Interleaved three phase Y-delta connected power converter | Jing-Yuan Lin, Kuan-Hung Chen, Yi-Feng Lin | 2023-01-10 |
| 11527534 | Gap-insulated semiconductor device | Jung-Chien Cheng, Shi Ning Ju, Kuo-Cheng Chiang, Chih-Hao Wang, Kuan-Lun Cheng | 2022-12-13 |
| 11462612 | Semiconductor device structure | Jung-Chien Cheng, Shi Ning Ju, Kuo-Cheng Chiang, Chih-Hao Wang, Kuan-Lun Cheng | 2022-10-04 |
| 11315925 | Uniform gate width for nanostructure devices | Jui-Chien Huang, Shih-Cheng Chen, Chih-Hao Wang, Kuo-Cheng Chiang, Zhi-Chang Lin +3 more | 2022-04-26 |
| 11302825 | Self-aligned spacers for multi-gate devices and method of fabrication thereof | Kuo-Cheng Ching, Shi Ning Ju, Kuan-Lun Cheng, Chih-Hao Wang | 2022-04-12 |
| 11296199 | Semiconductor devices and methods | Shi Ning Ju, Kuo-Cheng Chiang, Chih-Hao Wang | 2022-04-05 |
| 11296081 | Integration of silicon channel nanostructures and silicon-germanium channel nanostructures | Shi Ning Ju, Kuo-Cheng Chiang, Chih-Hao Wang, Kuan-Lun Cheng | 2022-04-05 |
| 11257903 | Method for manufacturing semiconductor structure with hybrid nanostructures | Wen-Ting Lan, Shi Ning Ju, Kuo-Cheng Chiang, Chih-Hao Wang, Ching-Wei Tsai +1 more | 2022-02-22 |
| 11222948 | Semiconductor structure and method of fabricating the semiconductor structure | Kuo-Cheng Chiang, Chih-Hao Wang, Shi Ning Ju, Jui-Chien Huang | 2022-01-11 |
| 11201225 | Structure and formation method of semiconductor device with stressor | Kuo-Cheng Chiang, Shi Ning Ju, Chih-Hao Wang | 2021-12-14 |
| 11121213 | Fin recess last process for FinFET fabrication | Kuo-Cheng Chiang, Shi Ning Ju | 2021-09-14 |
| 11121036 | Multi-gate device and related methods | Kuo-Cheng Ching, Huan-Chieh Su, Shi Ning Ju, Chih-Hao Wang | 2021-09-14 |
| 11114550 | Recessing STI to increase FIN height in FIN-first process | Kuo-Cheng Chiang | 2021-09-07 |
| 11075201 | Tuning tensile strain on FinFET | Kuo-Cheng Chiang, Zhi-Chang Lin, Ting-Hung Hsu, Jiun-Jia Huang | 2021-07-27 |
| 10998425 | FinFET structure and method for fabricating the same | Kuo-Cheng Chiang, Chao-Hsiung Wang, Chi-Wen Liu | 2021-05-04 |
| 10930794 | Self-aligned spacers for multi-gate devices and method of fabrication thereof | Kuo-Cheng Ching, Shi Ning Ju, Kuan-Lun Cheng, Chih-Hao Wang | 2021-02-23 |
| 10622464 | Integrated circuit structure with substrate isolation and un-doped channel | Kuo-Cheng Ching | 2020-04-14 |
| 10580961 | Method for determining a threshold voltage for obtaining a batch of sensing chips with increased sensitivity and method for increasing sensitivity of the batch of sensing chips | Chien-Chong Hong | 2020-03-03 |
| 10453842 | Tuning tensile strain on FinFET | Kuo-Cheng Ching, Zhi-Chang Lin, Ting-Hung Hsu, Jiun-Jia Huang | 2019-10-22 |
| 10269933 | Recessing STI to increase Fin height in Fin-first process | Kuo-Cheng Ching | 2019-04-23 |
| 10170592 | Integrated circuit structure with substrate isolation and un-doped channel | Kuo-Cheng Ching | 2019-01-01 |
| 10164068 | FinFET structure and method for fabricating the same | Kuo-Cheng Ching, Chao-Hsiung Wang, Chi-Wen Liu | 2018-12-25 |
| 10121851 | Fin recess last process for FinFET fabrication | Kuo-Cheng Ching, Shi Ning Ju | 2018-11-06 |