Issued Patents All Time
Showing 151–175 of 298 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11729990 | Capping layer over FET FeRAM to increase charge mobility | Rainer Yen-Chieh Huang, Hai-Ching Chen | 2023-08-15 |
| 11729983 | Peripheral circuitry under array memory device and method of fabricating thereof | Sheng-Chih Lai | 2023-08-15 |
| 11723284 | Top-interconnection metal lines for a memory array device and methods for forming the same | Yu-Feng Yin, Tai-Yen Peng, An-Shen Chang, Han-Ting Tsai, Qiang Fu | 2023-08-08 |
| 11723210 | High selectivity isolation structure for improving effectiveness of 3D memory fabrication | Tsu Ching Yang, Feng-Cheng Yang, Sheng-Chih Lai, Yu-Wei Jiang, Kuo-Chang Chiang +2 more | 2023-08-08 |
| 11723199 | Protective liner layers in 3D memory structure | Tsu Ching Yang, Sheng-Chih Lai, Yu-Wei Jiang, Kuo-Chang Chiang, Hung-Chang Sun +2 more | 2023-08-08 |
| 11721376 | Memory device, operation method of memory device and operation method of memory circuit | Hung-Li Chiang, Shy-Jay Lin, Tzu-Chiang Chen, Ming-Yuan Song, Hon-Sum Philip Wong | 2023-08-08 |
| 11721747 | Integrated circuit, transistor and method of fabricating the same | Yu-Wei Jiang, Sheng-Chih Lai, Feng-Cheng Yang | 2023-08-08 |
| 11723291 | Intercalated metal/dielectric structure for nonvolatile memory devices | Mauricio Manfrini, Gerben Doornbos, Marcus Johannes Henricus Van Dal | 2023-08-08 |
| 11716862 | Non-volatile memory with dual gated control | Katherine H. Chiang | 2023-08-01 |
| 11716855 | Three-dimensional memory device and method | Chia-Yu Ling, Katherine H. Chiang | 2023-08-01 |
| 11715546 | Memory array test method and system | Chien-Hao Huang, Katherine H. Chiang, Cheng-Yi Wu | 2023-08-01 |
| 11706928 | Memory device and method for fabricating the same | Rainer Yen-Chieh Huang, Hai-Ching Chen | 2023-07-18 |
| 11696453 | Vertical metal oxide semiconductor channel selector transistor and methods of forming the same | Yong-Jie Wu, Yen-Chung Ho, Pin-Cheng Hsu, Mauricio Manfrini | 2023-07-04 |
| 11690228 | Annealed seed layer to improve ferroelectric properties of memory layer | Song-Fu Liao, Rainer Yen-Chieh Huang, Hai-Ching Chen | 2023-06-27 |
| 11683988 | Semiconductor device | Tai-Yen Peng, Hui-Hsien Wei, Wei-Chih Wen, Pin-Ren Dai, Chien-Min Lee +2 more | 2023-06-20 |
| 11670715 | Semiconductor devices with ferroelectric layer and methods of manufacturing thereof | Yen-Chieh Huang, Po-Ting Lin, Hai-Ching Chen, Sai-Hooi Yeong, Yu-Ming Lin | 2023-06-06 |
| 11653501 | Ferroelectric memory device, manufacturing method of the ferroelectric memory device and semiconductor chip | Rainer Yen-Chieh Huang, Hai-Ching Chen, Yu-Ming Lin | 2023-05-16 |
| 11652041 | Semiconductor device and layout design thereof | Ting-Wei Chiang, Hui-Zhong Zhuang, Li-Chun Tien, Pin-Dai Sue | 2023-05-16 |
| 11652148 | Method of selective film deposition and semiconductor feature made by the method | Song-Fu Liao, Hai-Ching Chen | 2023-05-16 |
| 11647634 | Three-dimensional memory device and method | Feng-Cheng Yang, Meng-Han Lin, Han-Jong Chia, Sheng-Chen Wang | 2023-05-09 |
| 11637203 | Semiconductor device and manufacturing method of the same | Yu-Feng Yin, Chia-Jung Yu, Pin-Cheng Hsu | 2023-04-25 |
| 11636249 | Integrated circuit and layout method for standard cell structures | Sheng-Hsiung Chen, Fong-Yuan Chang, Ho Che Yu, Li-Chun Tien | 2023-04-25 |
| 11637098 | Pin modification for standard cells | Fong-Yuan Chang, Lee-Chung Lu, Po-Hsiang Huang, Chun-Chen Chen, Ting-Wei Chiang +2 more | 2023-04-25 |
| 11631661 | Integrated circuit having angled conductive feature | Tung-Heng Hsieh, Ting-Wei Chiang, Hui-Zhong Zhuang, Li-Chun Tien, Sheng-Hsiung Wang | 2023-04-18 |
| 11588107 | Integrated circuit structure | Tai-Yen Peng, Hui-Hsien Wei, Wei-Chih Wen, Pin-Ren Dai, Chien-Min Lee +2 more | 2023-02-21 |