Issued Patents All Time
Showing 126–137 of 137 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8624322 | High voltage device with a parallel resistor | Ru-Yi Su, Fu-Chih Yang, Ker Hsiao Huo, Jen-Hao Yeh, Chun-Wei Hsu | 2014-01-07 |
| 8598679 | Stacked and tunable power fuse | Chih-Chang Cheng, Ruey-Hsin Liu, Ru-Yi Su, Fu-Chih Yang | 2013-12-03 |
| 8587073 | High voltage resistor | Chih-Chang Cheng, Ruey-Hsin Liu, Chih-Wen Yao, Ru-Yi Su, Fu-Chih Yang | 2013-11-19 |
| 8575694 | Insulated gate bipolar transistor structure having low substrate leakage | Ker Hsiao Huo, Chih-Chang Cheng, Ru-Yi Su, Jen-Hao Yeh, Fu-Chih Yang | 2013-11-05 |
| 8507920 | Semiconductor structure and method of forming the same | Po-Chih Chen, Jiun-Lei Jerry Yu, Fu-Wei Yao, Chun-Wei Hsu, Fu-Chih Yang | 2013-08-13 |
| 8502326 | Gate dielectric formation for high-voltage MOS devices | Kong-Beng Thei, Jiun-Lei Jerry Yu, Chien-Chih Chou | 2013-08-06 |
| 8389348 | Mechanism of forming SiC crystalline on Si substrates to allow integration of GaN and Si electronics | Kong-Beng Thei, Jiun-Lei Jerry Yu, Hsiao-Chin Tuan, Alex Kalnitsky | 2013-03-05 |
| 8158475 | Gate electrodes of HVMOS devices having non-uniform doping concentrations | Ru-Yi Su, Puo-Yu Chiang, Jeng Gong, Tsung-Yi Huang, Chien-Chih Chou | 2012-04-17 |
| 8159029 | High voltage device having reduced on-state resistance | Ru-Yi Su, Puo-Yu Chiang, Jeng Gong, Tsung-Yi Huang, Chien-Chih Chou | 2012-04-17 |
| 7816744 | Gate electrodes of HVMOS devices having non-uniform doping concentrations | Ru-Yi Su, Puo-Yu Chiang, Jeng Gong, Tsung-Yi Huang, Chien-Chih Chou | 2010-10-19 |
| 6847061 | Elimination of implant damage during manufacture of HBT | Denny Tang, Chih-Min Chiang, Kuan-Lun Chang, Tsyr Shyang, Ruey-Hsin Liu | 2005-01-25 |
| 6703282 | Method of reducing NMOS device current degradation via formation of an HTO layer as an underlying component of a nitride-oxide sidewall spacer | Fu Ji Yang, Chien-Chih Chou, Ting-Jia Hu, Sheng Lin | 2004-03-09 |