Issued Patents All Time
Showing 526–550 of 937 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11387346 | Gate patterning process for multi-gate devices | Mao-Lin Huang, Lung-Kun Chu, Chung-Wei Hsu, Jia-Ni Yu, Kuo-Cheng Chiang | 2022-07-12 |
| 11387237 | Semiconductor component having a fin and an epitaxial contact structure over an epitaxial layer thereof | Kuo-Cheng Ching, Ching-Wei Tsai, Kuan-Lun Cheng | 2022-07-12 |
| 11387233 | Semiconductor device structure and methods of forming the same | Huan-Chieh Su, Chun-Yuan Chen, Pei-Yu Wang, Cheng-Chi Chuang | 2022-07-12 |
| 11387181 | Integrated circuits with backside power rails | Chih-Chao Chou, Kuo-Cheng Chiang, Shi Ning Ju, Wen-Ting Lan | 2022-07-12 |
| 11387140 | Enlarging contact area and process window for a contact via | Li-Zhen Yu, Cheng-Chi Chuang, Yu-Ming Lin, Lin-Yu Huang | 2022-07-12 |
| 11385420 | Photon source comprising a plurality of optical sources and an optical shell to receive the light emitted by the optical source | Imtiaz Majid, Peng-Chih Li | 2022-07-12 |
| 11387347 | Fin structures having varied fin heights for semiconductor device | Kuo-Cheng Chiang, Shi Ning Ju | 2022-07-12 |
| 11380682 | Integrated circuits with FinFET gate structures | Kuo-Cheng Ching, Huan-Chieh Su, Zhi-Chang Lin | 2022-07-05 |
| 11380783 | Structure and method for FinFET device with buried SiGe oxide | Kuo-Cheng Chiang, Carlos H. Diaz, Zhiqiang Wu | 2022-07-05 |
| 11380768 | Semiconductor device and manufacturing method thereof | Shih-Cheng Chen, Chun-Hsiung Lin | 2022-07-05 |
| 11380591 | Method for manufacturing nanostructure with various widths | Kuo-Cheng Ching, Shi Ning Ju, Kuan-Lun Cheng | 2022-07-05 |
| 11374093 | Semiconductor device structure and methods of forming the same | Lin-Yu Huang, Li-Zhen Yu, Cheng-Chi Chuang, Kuan-Lun Cheng | 2022-06-28 |
| 11374105 | Nanosheet device with dipole dielectric layer and methods of forming the same | Chung-Wei Hsu, Kuo-Cheng Chiang, Lung-Kun Chu, Mao-Lin Huang, Jia-Ni Yu | 2022-06-28 |
| 11362213 | Method for manufacturing a FinFET device with a backside power rail and a backside self-aligned via by etching an extended source trench | Shi Ning Ju, Kuo-Cheng Chiang, Kuan-Lun Cheng | 2022-06-14 |
| 11362191 | Semiconductor device and method for making the same | Chi-Yi Chuang, Ching-Wei Tsai, Kuan-Lun Cheng | 2022-06-14 |
| 11362001 | Method for manufacturing nanostructures with various widths | Hsiao-Han Liu, Kuo-Cheng Chiang, Shi Ning Ju, Kuan-Lun Cheng | 2022-06-14 |
| 11361986 | Using a liner layer to enlarge process window for a contact via | Li-Zhen Yu, Cheng-Chi Chuang, Yu-Ming Lin, Lin-Yu Huang | 2022-06-14 |
| 11355611 | Multi-gate device and method of fabrication thereof | Kuo-Cheng Ching, Ching-Fang Huang, Wen-Hsing Hsieh, Ying-Keung Leung, Carlos H. Diaz | 2022-06-07 |
| 11355603 | Methods and structures of novel contact feature | Wei-Hao Wu, Chia-Hao Chang, Jia-Chuan You, Yi-Hsiung Lin, Zhi-Chang Lin +2 more | 2022-06-07 |
| 11355601 | Semiconductor devices with backside power rail and backside self-aligned via | Kuo-Cheng Chiang, Shi Ning Ju, Kuan-Lun Cheng, Cheng-Chi Chuang | 2022-06-07 |
| 11355398 | Semiconductor device structure and methods of forming the same | Kuan-Ting Pan, Kuo-Cheng Chiang, Shang-Wen Chang, Ching-Wei Tsai, Kuan-Lun Cheng | 2022-06-07 |
| 11355396 | Method of forming a semiconductor structure including laterally etching semiconductor material in fin recess region and depositing metal gate therein | Kuo-Cheng Ching, Zhi-Chang Lin, Shi Ning Ju, Kuan-Ting Pan | 2022-06-07 |
| 11349016 | Fin field effect transistor (FinFET) with a liner layer | Kuo-Cheng Ching, Kuan-Ting Pan, Shi Ning Ju | 2022-05-31 |
| 11349004 | Backside vias in semiconductor device | Li-Zhen Yu, Huan-Chieh Su, Lin-Yu Huang, Cheng-Chi Chuang | 2022-05-31 |
| 11348836 | Semiconductor structure with nanostructure and method for manufacturing the same | Pei-Hsun Wang, Chun-Hsiung Lin, Chih-Chao Chou | 2022-05-31 |