Issued Patents All Time
Showing 176–200 of 262 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6773973 | Semiconductor transistor having a polysilicon emitter and methods of making the same | Sudarsan Uppili, Sang-Hoon Park | 2004-08-10 |
| 6767798 | Method of forming self-aligned NPN transistor with raised extrinsic base | Alexei Shatalov, Michael Rowlandson, Sang-Hoon Park, Robert F. Scheer, Fanling H. Yang | 2004-07-27 |
| 6686250 | Method of forming self-aligned bipolar transistor | Michael Rowlandson, Fanling H. Yang, Sang-Hoon Park, Robert F. Scheer | 2004-02-03 |
| 6645803 | Method for modifying the doping level of a silicon layer | Arnaud Lepert | 2003-11-11 |
| 6593200 | Method of forming an integrated inductor and high speed interconnect in a planarized process with shallow trench isolation | Dmitri A. Choutov, Geoffrey C. Stutzin, Robert F. Scheer | 2003-07-15 |
| 6593640 | Bipolar transistor and methods of forming bipolar transistors | Sudarsan Uppili | 2003-07-15 |
| 6531783 | Method of via formation for multilevel interconnect integrated circuits | — | 2003-03-11 |
| 6525397 | Extended drain MOSFET for programming an integrated fuse element to high resistance in low voltage process technology | Pavel Poplevine, Albert Bergemont | 2003-02-25 |
| 6492237 | Method of forming an NPN device | Sang-Hoon Park, Robert F. Scheer | 2002-12-10 |
| 6489217 | Method of forming an integrated circuit on a low loss substrate | Robert F. Scheer | 2002-12-03 |
| 6483931 | Electrostatic discharge protection of a capacitve type fingerprint sensing array | Alan Kramer | 2002-11-19 |
| 6479394 | Method of low-selective etching of dissimilar materials having interfaces at non-perpendicular angles to the etch propagation direction | Dmitri A. Choutov, Geoffrey C. Stutzin | 2002-11-12 |
| 6475873 | Method of forming laser trimmable thin-film resistors in a fully planarized integrated circuit technology | Robert F. Scheer, Joseph P. Ellul | 2002-11-05 |
| 6420217 | Method of an apparatus for programming an integrated fuse element to high resistance in low voltage technology | Pavel Poplevine, Albert Bergemont | 2002-07-16 |
| 6384398 | CMOS compatible pixel cell that utilizes a gated diode to reset the cell | Albert Bergemont, Pavel Poplevine | 2002-05-07 |
| 6380054 | Schottky diode with reduced size | Pavel Poplevine, Albert Bergemont | 2002-04-30 |
| 6380571 | CMOS compatible pixel cell that utilizes a gated diode to reset the cell | Albert Bergemont, Pavel Poplevine | 2002-04-30 |
| 6368917 | Methods of fabricating floating gate semiconductor device with reduced erase voltage | Albert Bergemont | 2002-04-09 |
| 6365463 | Method for forming a high-precision analog transistor with a low threshold voltage roll-up and a digital transistor with a high threshold voltage roll-up | Albert Bergemont | 2002-04-02 |
| 6362050 | Method for forming a non-volatile memory cell that eliminates substrate trenching | Albert Bergemont | 2002-03-26 |
| 6362023 | Dielectric-based anti-fuse cell with polysilicon contact plug and method for its manufacture | Albert Bergemont | 2002-03-26 |
| 6358809 | Method of modifying properties of deposited thin film material | Glenn Nobinger, Melvin C. Schmidt, Jonathan François Cornelis Herman, Viktor Zekeriya, Vijaykumar Ullal +2 more | 2002-03-19 |
| 6327187 | EPROM and flash memory cells with source-side injection and a gate dielectric that traps hot electrons during programming | Albert Bergemont | 2001-12-04 |
| 6303413 | Method of forming a shallow and deep trench isolation (SDTI) suitable for silicon on insulator (SOI) substrates | Dmitri A. Choutov, Robert F. Scheer, Fanling H. Yang, Thomas W. Dobson, Tadanori Yamaguchi +2 more | 2001-10-16 |
| 6277724 | Method for forming an array of sidewall-contacted antifuses having diffused bit lines | Albert Bergemont | 2001-08-21 |