Issued Patents All Time
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6303413 | Method of forming a shallow and deep trench isolation (SDTI) suitable for silicon on insulator (SOI) substrates | Alexander Kalnitsky, Dmitri A. Choutov, Robert F. Scheer, Fanling H. Yang, Thomas W. Dobson +2 more | 2001-10-16 |
| 4994400 | Method of fabricating a semiconductor device using a tri-layer structure and conductive sidewalls | Yeou-Chong S. Yu, Carol A. Hacherl, Evan E. Patton | 1991-02-19 |
| 4902640 | High speed double polycide bipolar/CMOS integrated circuit process | Jack Sachitano, Hee K. Park, Paul K. Boyer, Gregory C. Eiden | 1990-02-20 |
| 4876214 | Method for fabricating an isolation region in a semiconductor substrate | Evan E. Patton, Eric Lane, Simon Yeou-Chong Yu | 1989-10-24 |
| 4486266 | Integrated circuit method | — | 1984-12-04 |
| 4477310 | Process for manufacturing MOS integrated circuit with improved method of forming refractory metal silicide areas | Hee K. Park | 1984-10-16 |
| 4261761 | Method of manufacturing sub-micron channel width MOS transistor | Shuichi Sato, Arthur D. Ritchie | 1981-04-14 |
| 4229756 | Ultra high speed complementary MOS device | Shuichi Sato, Jack Sachitano | 1980-10-21 |
| 4228447 | Submicron channel length MOS inverter with depletion-mode load transistor | Shuichi Sato | 1980-10-14 |
| 4217599 | Narrow channel MOS devices and method of manufacturing | Shuichi Sato, Arthur D. Ritchie | 1980-08-12 |