Issued Patents All Time
Showing 1–25 of 36 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12399218 | PORs testing in multiple power domain devices | Mayankkumar Hareshbhai Niranjani, Gourav Garg | 2025-08-26 |
| 12366605 | Area, cost, and time-effective scan coverage improvement | Umesh Chandra Srivastava, Shiv Kumar Vats, Manish Sharma | 2025-07-22 |
| 12360161 | Scan circuit and method | Shiv Kumar Vats, Tripti Gupta | 2025-07-15 |
| 12345764 | Test pattern generation using multiple scan enables | Shiv Kumar Vats, Umesh Chandra Srivastava | 2025-07-01 |
| 12272416 | ATPG testing method for latch based memories, for area reduction | Balwinder Singh Soni, Avneep Kumar Goyal | 2025-04-08 |
| 12203982 | System and method for parallel testing of electronic device | Rajesh Narwal, Srinivas Dhulipalla | 2025-01-21 |
| 12146911 | TVF transition coverage with self-test and production-test time reduction | Manish Sharma, Jeena Mary George, Umesh Chandra Srivastava | 2024-11-19 |
| 12020760 | ATPG testing method for latch based memories, for area reduction | Balwinder Singh Soni, Avneep Kumar Goyal | 2024-06-25 |
| 11983025 | Reset and safe state logic generation in dual power flow devices | Mayankkumar Hareshbhai Niranjani, Dhulipalla Phaneendra Kumar, Gourav Garg, Sourabh Banzal | 2024-05-14 |
| 11835991 | Self-test controller, and associated method | Amulya Pandey, Balwinder Singh Soni, Amritanshu Anand | 2023-12-05 |
| 11726140 | Scan circuit and method | Shiv Kumar Vats, Tripti Gupta | 2023-08-15 |
| 11714131 | Circuit and method for scan testing | Manish Sharma, Shiv Kumar Vats, Umesh Chandra Srivastava | 2023-08-01 |
| 11680982 | Automatic test pattern generation circuitry in multi power domain system on a chip | Manish Sharma, Tripti Gupta | 2023-06-20 |
| 11557364 | ATPG testing method for latch based memories, for area reduction | Balwinder Singh Soni, Avneep Kumar Goyal | 2023-01-17 |
| 11550348 | Methods and devices for bypassing a voltage regulator | Mayankkumar Hareshbhai Niranjani, Gourav Garg | 2023-01-10 |
| 11513544 | Reset and safe state logic generation in dual power flow devices | Mayankkumar Hareshbhai Niranjani, Dhulipalla Phaneendra Kumar, Gourav Garg, Sourabh Banzal | 2022-11-29 |
| 11442108 | Isolation logic test circuit and associated test method | Gourav Garg, Dhulipalla Phaneendra Kumar | 2022-09-13 |
| 11340292 | System and method for parallel testing of electronic device | Rajesh Narwal, Srinivas Dhulipalla | 2022-05-24 |
| 11119153 | Isolation enable test coverage for multiple power domains | — | 2021-09-14 |
| 11041905 | Combinatorial serial and parallel test access port selection in a JTAG interface | Manish Sharma | 2021-06-22 |
| 10996266 | System and method for testing voltage monitors | Rajesh Narwal, Srinivas Dhulipalla | 2021-05-04 |
| 10890619 | Sequential test access port selection in a JTAG interface | Manish Sharma | 2021-01-12 |
| 10802077 | Test circuit for dynamic checking for faults on functional and BIST clock paths to memory in both ATPG and LBIST modes | Shiv Kumar Vats, Himanshu | 2020-10-13 |
| 10747282 | Test circuit for electronic device permitting interface control between two supply stacks in a production test of the electronic device | Srinivas Dhulipalla, Sandip Atal | 2020-08-18 |
| 10620267 | Circuitry for testing non-maskable voltage monitor for power management block | Srinivas Dhulipalla | 2020-04-14 |