Issued Patents All Time
Showing 1–6 of 6 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11983025 | Reset and safe state logic generation in dual power flow devices | Venkata Narayanan Srinivasan, Mayankkumar Hareshbhai Niranjani, Gourav Garg, Sourabh Banzal | 2024-05-14 |
| 11860993 | Dynamic randomization of password challenge | — | 2024-01-02 |
| 11513544 | Reset and safe state logic generation in dual power flow devices | Venkata Narayanan Srinivasan, Mayankkumar Hareshbhai Niranjani, Gourav Garg, Sourabh Banzal | 2022-11-29 |
| 11442108 | Isolation logic test circuit and associated test method | Venkata Narayanan Srinivasan, Gourav Garg | 2022-09-13 |
| 11281795 | Hierarchical random scrambling of secure data storage resulting in randomness across chips and on power on resets of individual chips | — | 2022-03-22 |
| 11227046 | Dynamic randomization of password challenge | — | 2022-01-18 |