Issued Patents All Time
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12272416 | ATPG testing method for latch based memories, for area reduction | Venkata Narayanan Srinivasan, Avneep Kumar Goyal | 2025-04-08 |
| 12020760 | ATPG testing method for latch based memories, for area reduction | Venkata Narayanan Srinivasan, Avneep Kumar Goyal | 2024-06-25 |
| 11835991 | Self-test controller, and associated method | Amulya Pandey, Amritanshu Anand, Venkata Narayanan Srinivasan | 2023-12-05 |
| 11557364 | ATPG testing method for latch based memories, for area reduction | Venkata Narayanan Srinivasan, Avneep Kumar Goyal | 2023-01-17 |
| 10944407 | Source synchronous interface with selectable delay on source and delay on destination control | Dinesh Chandra Joshi | 2021-03-09 |
| 10393804 | Clock selection circuit and test clock generation circuit for LBIST and ATPG test circuit | Venkata Narayanan Srinivasan, Nimit Endlay | 2019-08-27 |
| 10228420 | Clock selection circuit and test clock generation circuit for LBIST and ATPG test circuit | Venkata Narayanan Srinivasan, Nimit Endlay | 2019-03-12 |
| 8644447 | System and a method for generating time bases in low power domain | Chandra Prakash | 2014-02-04 |