Issued Patents All Time
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12393505 | Reset circuitry providing independent reset signal for trace and debug logic | Amritanshu Anand, Satinder Singh Malhi | 2025-08-19 |
| 12298872 | Glitch suppression apparatus and method | — | 2025-05-13 |
| 12272416 | ATPG testing method for latch based memories, for area reduction | Venkata Narayanan Srinivasan, Balwinder Singh Soni | 2025-04-08 |
| 12210609 | Central controller for multiple development ports | Thomas Szurmant | 2025-01-28 |
| 12020760 | ATPG testing method for latch based memories, for area reduction | Venkata Narayanan Srinivasan, Balwinder Singh Soni | 2024-06-25 |
| 11914499 | Systems and methods for preparing trace data | Thomas Szurmant, Misaele Marletti, Alessandro Daolio | 2024-02-27 |
| 11892505 | Debug and trace circuit in lockstep architectures, associated method, processing system, and apparatus | Anubhav Arora | 2024-02-06 |
| 11687428 | Glitch suppression apparatus and method | — | 2023-06-27 |
| 11557364 | ATPG testing method for latch based memories, for area reduction | Venkata Narayanan Srinivasan, Balwinder Singh Soni | 2023-01-17 |
| 11360143 | High speed debug-delay compensation in external tool | Deepak Baranwal, Thomas Szurmant, Nicolas Bernard Grossier | 2022-06-14 |
| 10924091 | Immediate fail detect clock domain crossing synchronizer | — | 2021-02-16 |