Issued Patents All Time
Showing 26–36 of 36 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10527672 | Voltage regulator bypass circuitry usable during device testing operations | Srinivas Dhulipalla | 2020-01-07 |
| 10502784 | Voltage level monitoring of an integrated circuit for production test and debug | Satinder Singh Malhi | 2019-12-10 |
| 10495690 | Combinatorial serial and parallel test access port selection in a JTAG interface | Manish Sharma | 2019-12-03 |
| 10393804 | Clock selection circuit and test clock generation circuit for LBIST and ATPG test circuit | Nimit Endlay, Balwinder Singh Soni | 2019-08-27 |
| 10386411 | Sequential test access port selection in a JTAG interface | Manish Sharma | 2019-08-20 |
| 10228420 | Clock selection circuit and test clock generation circuit for LBIST and ATPG test circuit | Nimit Endlay, Balwinder Singh Soni | 2019-03-12 |
| 10151797 | Logic built-in self-test (LBIST) with pipeline scan enable launch on shift (LOS) flip-flop circuit | Tripti Gupta | 2018-12-11 |
| 10048315 | Stuck-at fault detection on the clock tree buffers of a clock source | — | 2018-08-14 |
| 9941875 | Testing of power on reset (POR) and unmaskable voltage monitors | Srinivas Dhulipalla | 2018-04-10 |
| 9698771 | Testing of power on reset (POR) and unmaskable voltage monitors | Srinivas Dhulipalla | 2017-07-04 |
| 9335375 | Integrated device test circuits and methods | — | 2016-05-10 |