Issued Patents All Time
Showing 151–175 of 187 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8958249 | Partitioned erase and erase verification in non-volatile memory | Chun-Hung Lai, Shih-Chung Lee, Ken Oowada, Masaaki Higashitani | 2015-02-17 |
| 8953386 | Dynamic bit line bias for programming non-volatile memory | Ken Oowada, Masaaki Higashitani, Man Lung Mui | 2015-02-10 |
| 8908441 | Double verify method in multi-pass programming to suppress read noise | Ken Oowada, Genki Sano, Masaaki Higashitani | 2014-12-09 |
| 8902668 | Double verify method with soft programming to suppress read noise | Ken Oowada, Genki Sano, Masaaki Higashitani | 2014-12-02 |
| 8885404 | Non-volatile storage system with three layer floating gate | Shinji Sato, Masaaki Higashitani, Dengtao Zhao, Sanghyun Lee | 2014-11-11 |
| 8885420 | Erase for non-volatile storage | Ken Oowada | 2014-11-11 |
| 8861282 | Method and apparatus for program and erase of select gate transistors | Yan Li, Masaaki Higashitani, Mohan Dunga | 2014-10-14 |
| 8787088 | Optimized erase operation for non-volatile memory with partially programmed block | Ken Oowada, Koichi Nishimura, Yingda Dong | 2014-07-22 |
| 8773902 | Channel boosting using secondary neighbor channel coupling in non-volatile memory | Shinji Sato, Fumiko Yano | 2014-07-08 |
| 8743606 | Natural threshold voltage distribution compaction in non-volatile memory | Jeffrey W. Lutze | 2014-06-03 |
| 8638608 | Selected word line dependent select gate voltage during program | Chun-Hung Lai, Shinji Sato, Gerrit Jan Hemink | 2014-01-28 |
| 8638606 | Substrate bias during program of non-volatile storage | Dengtao Zhao, Guirong Liang | 2014-01-28 |
| 8611157 | Program temperature dependent read | — | 2013-12-17 |
| 8611148 | Data state-dependent channel boosting to reduce channel-to-floating gate coupling in memory | Jeffrey W. Lutze, Grishma Shah | 2013-12-17 |
| 8576624 | On chip dynamic read for non-volatile storage | Dana Lee, Jeffrey W. Lutze | 2013-11-05 |
| 8542535 | Controlling select gate voltage during erase to improve endurance in non volatile memory | Jeffrey W. Lutze | 2013-09-24 |
| 8537611 | Natural threshold voltage distribution compaction in non-volatile memory | Jeffrey W. Lutze | 2013-09-17 |
| 8520448 | Sequential programming of sets of non-volatile elements to improve boost voltage clamping | Jeffrey W. Lutze | 2013-08-27 |
| 8451667 | Pair bit line programming to improve boost voltage clamping | Jeffrey W. Lutze | 2013-05-28 |
| 8406053 | On chip dynamic read for non-volatile storage | Dana Lee, Jeffrey W. Lutze | 2013-03-26 |
| 8385132 | Alternate bit line bias during programming to reduce channel to floating gate coupling in memory | Jeffrey W. Lutze | 2013-02-26 |
| 8369149 | Multi-step channel boosting to reduce channel to floating gate coupling in memory | Jeffrey W. Lutze, Henry Chin | 2013-02-05 |
| 8320177 | Programming memory with reduced pass voltage disturb and floating gate-to-control gate leakage | Henry Chin | 2012-11-27 |
| 8310870 | Natural threshold voltage distribution compaction in non-volatile memory | Jeffrey W. Lutze | 2012-11-13 |
| 8274838 | Programming non-volatile memory with bit line voltage step up | Jeffrey W. Lutze | 2012-09-25 |