Issued Patents All Time
Showing 176–187 of 187 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8248850 | Data recovery for non-volatile memory based on count of data state-specific fails | Jeffrey W. Lutze, Yan Li | 2012-08-21 |
| 8223556 | Programming non-volatile memory with a reduced number of verify operations | Gerrit Jan Hemink | 2012-07-17 |
| 8169822 | Data state-dependent channel boosting to reduce channel-to-floating gate coupling in memory | Jeffrey W. Lutze, Grishma Shah | 2012-05-01 |
| 8134871 | Programming memory with reduced pass voltage disturb and floating gate-to-control gate leakage | Henry Chin | 2012-03-13 |
| 8130556 | Pair bit line programming to improve boost voltage clamping | Jeffrey W. Lutze | 2012-03-06 |
| 8130551 | Extra dummy erase pulses after shallow erase-verify to avoid sensing deep erased threshold voltage | Ken Oowada, Yingda Dong | 2012-03-06 |
| 8081514 | Partial speed and full speed programming for non-volatile memory using floating bit lines | Man Lung Mui, Yingda Dong, Binh Lee | 2011-12-20 |
| 8051240 | Compensating non-volatile storage using different pass voltages during program-verify and read | Jeffrey W. Lutze | 2011-11-01 |
| 8004900 | Controlling select gate voltage during erase to improve endurance in non-volatile memory | Jeffrey W. Lutze | 2011-08-23 |
| 7876611 | Compensating for coupling during read operations in non-volatile storage | Jeffrey W. Lutze, Yingda Dong, Henry Chin, Toru Ishigaki | 2011-01-25 |
| 7839687 | Multi-pass programming for memory using word line coupling | Jeffrey W. Lutze | 2010-11-23 |
| 7800956 | Programming algorithm to reduce disturb with minimal extra time penalty | Dana Lee, Yingda Dong | 2010-09-21 |