Issued Patents All Time
Showing 51–75 of 86 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8417961 | Apparatus and method for implementing instruction support for performing a cyclic redundancy check (CRC) | Christopher H. Olson, Lawrence Spracklen | 2013-04-09 |
| 8412911 | System and method to invalidate obsolete address translations | Paul J. Jordan, Mark Luttrell, Zeid H. Samoail | 2013-04-02 |
| 8356185 | Apparatus and method for local operand bypassing for cryptographic instructions | Christopher H. Olson, Robert T. Golla | 2013-01-15 |
| 8335911 | Dynamic allocation of resources in a threaded, heterogeneous processor | Robert T. Golla | 2012-12-18 |
| 8301865 | System and method to manage address translation requests | Paul J. Jordan, Mark Luttrell, Zeid H. Samoail, Robert T. Golla | 2012-10-30 |
| 8195923 | Methods and mechanisms to support multiple features for a number of opcodes | Lawrence Spracklen, Christopher H. Olson, Robert T. Golla | 2012-06-05 |
| 8190864 | APIC implementation for a highly-threaded x86 processor | Paul J. Jordan | 2012-05-29 |
| 7937556 | Minimizing TLB comparison size | Paul J. Jordan, Manish K. Shah | 2011-05-03 |
| 7795899 | Enabling on-chip features via efuses | Christopher H. Olson, Thomas A. Ziaja, Lawrence Spracklen | 2010-09-14 |
| 7779238 | Method and apparatus for precisely identifying effective addresses associated with hardware events | Nicolai Kosche, Paul J. Jordan | 2010-08-17 |
| 7747771 | Register access protocol in a multihreaded multi-core processor | Manish K. Shah, Robert T. Golla, Mark Luttrell | 2010-06-29 |
| 7720219 | Apparatus and method for implementing a hash algorithm word buffer | Christopher H. Olson, Leonard Rarick | 2010-05-18 |
| 7711955 | Apparatus and method for cryptographic key expansion | Christopher H. Olson, Leonard Rarick | 2010-05-04 |
| 7702887 | Performance instrumentation in a fine grain multithreaded multicore processor | Paul J. Jordan, Yue Chang | 2010-04-20 |
| 7684563 | Apparatus and method for implementing a unified hash algorithm pipeline | Christopher H. Olson, Leonard Rarick | 2010-03-23 |
| 7685354 | Multiple-core processor with flexible mapping of processor cores to cache banks | Ricky C. Hetherington, Manish K. Shah, Bikram Saha | 2010-03-23 |
| 7620821 | Processor including general-purpose and cryptographic functionality in which cryptographic operations are visible to user-specified software | Christopher H. Olson, Leonard Rarick | 2009-11-17 |
| 7570760 | Apparatus and method for implementing a block cipher algorithm | Christopher H. Olson | 2009-08-04 |
| 7533248 | Multithreaded processor including a functional unit shared between multiple requestors and arbitration therefor | Robert T. Golla | 2009-05-12 |
| 7454666 | Real-time address trace generation | Paul J. Jordan, Joseph T. Rahmeh | 2008-11-18 |
| 7454590 | Multithreaded processor having a source processor core to subsequently delay continued processing of demap operation until responses are received from each of remaining processor cores | Paul J. Jordan, Manish K. Shah | 2008-11-18 |
| 7401206 | Apparatus and method for fine-grained multithreading in a multipipelined processor core | Ricky C. Hetherington, Robert T. Golla | 2008-07-15 |
| 7392399 | Methods and systems for efficiently integrating a cryptographic co-processor | Paul J. Jordan, Michael Wong, Leslie D. Kohn | 2008-06-24 |
| 7383415 | Hardware demapping of TLBs shared by multiple threads | Paul J. Jordan, Manish K. Shah | 2008-06-03 |
| 7370243 | Precise error handling in a fine grain multithreaded multicore processor | Ricky C. Hetherington, Paul J. Jordan, Robert M. Maier | 2008-05-06 |