Issued Patents All Time
Showing 26–50 of 59 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7678655 | Spacer layer etch method providing enhanced microelectronic device performance | Ju-Wang Hsu, Yi-Chun Huang, Shien-Yang Wu, Yung-Shun Chen, Tung-Heng Shie +3 more | 2010-03-16 |
| 7652536 | Amplifier circuit with internal zeros | Jing-Meng Liu, An-Tung Chen, Pao-Chuan Lin | 2010-01-26 |
| 7557553 | Power supply circuit and control method thereof | Jing-Meng Liu | 2009-07-07 |
| 7535032 | Single-chip common-drain JFET device and its applications | Liang-Pin Tai, Jing-Meng Liu | 2009-05-19 |
| 7436640 | Booster power management integrated circuit chip with ESD protection between output pads thereof | Jing-Meng Liu, Chiang-Yung Ku | 2008-10-14 |
| 7382172 | Level shift circuit and method for the same | Pao-Chuan Lin, An-Tung Chen, Jing-Meng Liu | 2008-06-03 |
| 7327124 | Control apparatus and method for a boost-inverting converter | Jing-Meng Liu, Chung-Lung Pai, Wei-Hsin Wei | 2008-02-05 |
| 7248084 | Method for determining switching state of a transistor-based switching device | Chun-Yen Huang, Jing-Meng Liu, Chung-Lung Pai, Shih-Hui Chen, Yang-Ping Hung | 2007-07-24 |
| 7132717 | Power metal oxide semiconductor transistor layout with lower output resistance and high current limit | Chun-Yen Huang, Chung-Lung Pai, Jing-Meng Liu | 2006-11-07 |
| 6885214 | Method for measuring capacitance-voltage curves for transistors | Shien-Yang Wu, Yung-Shun Chen, Kuan-Yao Wang, Sun-Jay Chang | 2005-04-26 |
| 6828198 | System-on-chip (SOC) solutions with multiple devices by multiple poly gate trimming process | Shien-Yang Wu, Yung-Shun Chen, Tung-Heng Shie, Yuan-Hung Chiu | 2004-12-07 |
| 6765772 | Electrostatic discharge protection device | Jian-Hsing Lee | 2004-07-20 |
| 6747857 | Clamping circuit for stacked NMOS ESD protection | Jian-Hsing Lee, Jiaw-Ren Shih | 2004-06-08 |
| 6724036 | Stacked-gate flash memory cell with folding gate and increased coupling ratio | Chia-Ta Hsieh, Di-Son Kuo, Yai-Fen Lin, Chrong-Jung Lin, Jong Chen | 2004-04-20 |
| 6653709 | CMOS output circuit with enhanced ESD protection using drain side implantation | Yi-Hsu Wu, Jian-Hsing Lee, Boon-Khim Liew | 2003-11-25 |
| 6582995 | Method for fabricating a shallow ion implanted microelectronic structure | Ting-Hua Hsieh, Carlos H. Diaz | 2003-06-24 |
| 6495880 | Method to fabricate a flash memory cell with a planar stacked gate | Chrong-Jung Lin, Jong Chen, Di-Son Kuo | 2002-12-17 |
| 6444511 | CMOS output circuit with enhanced ESD protection using drain side implantation | Yi-Hsu Wu, Jian-Hsing Lee, Boon-Khim Liew | 2002-09-03 |
| 6414532 | Gate ground circuit approach for I/O ESD protection | Jian-Hsing Lee, Yi-Hsun Wu, Mau-Lin Wu | 2002-07-02 |
| 6348382 | Integration process to increase high voltage breakdown performance | Chrong-Jung Lin, Jong Chen, Wen-Ting Chu | 2002-02-19 |
| 6297098 | Tilt-angle ion implant to improve junction breakdown in flash memory application | Chrong-Jung Lin, Jong Chen, Wen-Ting Chu | 2001-10-02 |
| 6261905 | Flash memory structure with stacking gate formed using damascene-like structure | Jong Chen, Chrong-Jong Lin, Wen-Ting Chu | 2001-07-17 |
| 6251744 | Implant method to improve characteristics of high voltage isolation and high voltage breakdown | Chrong-Jung Lin, Jong Chen, Wen-Ting Chu, Hung-Cheng Sung, Di-Son Kuo | 2001-06-26 |
| 6246075 | Test structures for monitoring gate oxide defect densities and the plasma antenna effect | Jian-Hsing Lee, Di-Son Kuo | 2001-06-12 |
| 6190969 | Method to fabricate a flash memory cell with a planar stacked gate | Chrong-Jung Lin, Jong Chen, Di-Son Kuo | 2001-02-20 |