Issued Patents All Time
Showing 51–59 of 59 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6153494 | Method to increase the coupling ratio of word line to floating gate by lateral coupling in stacked-gate flash | Chia-Ta Hsieh, Di-Son Kuo, Yai-Fen Lin, Chrong-Jung Lin, Jong Chen | 2000-11-28 |
| 6133096 | Process for simultaneously fabricating a stack gate flash memory cell and salicided periphereral devices | Jong Chen, Chrong-Jung Lin, Di-Son Kuo | 2000-10-17 |
| 6130168 | Using ONO as hard mask to reduce STI oxide loss on low voltage device in flash or EPROM process | Wen-Ting Chu, Di-Son Kuo, Chrong-Jung Lin, Jong Chen | 2000-10-10 |
| 6127227 | Thin ONO thickness control and gradual gate oxidation suppression by b. N.su2 treatment in flash memory | Chrong-Jung Lin, Jong Chen, Di-Son Kuo | 2000-10-03 |
| 6124177 | Method for making deep sub-micron mosfet structures having improved electrical characteristics | Chrong-Jung Lin, Jong Chen, Wen-Ting Chu | 2000-09-26 |
| 6074915 | Method of making embedded flash memory with salicide and sac structure | Jong Chen, Chrong-Jung Lin, Di-Son Kuo | 2000-06-13 |
| 6037223 | Stack gate flash memory cell featuring symmetric self aligned contact structures | Chrong-Jung Lin, Jong Chen, Di-Son Kuo | 2000-03-14 |
| 6028324 | Test structures for monitoring gate oxide defect densities and the plasma antenna effect | Jian-Hsing Lee, Di-Son Kuo | 2000-02-22 |
| 6001687 | Process for forming self-aligned source in flash cell using SiN spacer as hard mask | Wen-Ting Chu, Di-Son Kuo, Chrong-Jung Lin, Jong Chen | 1999-12-14 |