Issued Patents All Time
Showing 26–50 of 160 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11922066 | Stacked device communication | Michael Raymond Miller, Steven C. Woo | 2024-03-05 |
| 11908515 | 2T-1R architecture for resistive ram | Deepak C. Sekar, Wayne F. Ellis, Brent Haukness, Gary B. Bronner | 2024-02-20 |
| 11894093 | Stacked DRAM device and method of manufacture | — | 2024-02-06 |
| 11868619 | Partial array refresh timing | Liji Gopalakrishnan, John Eric Linstadt | 2024-01-09 |
| 11842762 | System application of DRAM component with cache mode | Frederick A. Ware, Michael Raymond Miller, Collins Williams | 2023-12-12 |
| 11842761 | Memory system with multiple open rows per bank | John Eric Linstadt, Liji Gopalakrishnan | 2023-12-12 |
| 11822822 | Memory component having internal read-modify-write operation | Frederick A. Ware | 2023-11-21 |
| 11823734 | Dram device with multiple voltage domains | — | 2023-11-21 |
| 11804250 | Memory with deferred fractional row activation | James E. Harris, Frederick A. Ware, Ian Shaeffer | 2023-10-31 |
| 11790973 | Memory component with efficient write operations | Frederick A. Ware, John Eric Linstadt, Brent Haukness, Kenneth L. Wright | 2023-10-17 |
| 11775213 | Stacked memory device with paired channels | — | 2023-10-03 |
| 11653476 | Memory subsystem for a cryogenic digital system | Frederick A. Ware, John Eric Linstadt | 2023-05-16 |
| 11646090 | DRAM retention test method for dynamic error correction | Ely Tsern, Frederick A. Ware, Suresh Rajan | 2023-05-09 |
| 11645212 | Dynamic processing speed | Steven C. Woo, Joseph James Tringali, Pooneh Safayenikoo | 2023-05-09 |
| 11600349 | Testing through-silicon-vias | William N. Ng, Frederick A. Ware | 2023-03-07 |
| 11568929 | 2T-1R architecture for resistive RAM | Deepak C. Sekar, Wayne F. Ellis, Brent Haukness, Gary B. Bronner | 2023-01-31 |
| 11347441 | Memory component having internal read-modify-write operation | Frederick A. Ware | 2022-05-31 |
| 11341086 | Compute accelerator with 3D data flows | Amogh Agrawal, Steven C. Woo | 2022-05-24 |
| 11284034 | Fractional-readout oversampled image sensor | Jay Endsley, Craig M. Smith, Michael Guidash, Alexander Schneider | 2022-03-22 |
| 11270741 | Deferred fractional memory row activation | James E. Harris, Frederick A. Ware, Ian Shaeffer | 2022-03-08 |
| 11257539 | Reduced transport energy in a memory system | Frederick A. Ware, John Eric Linstadt | 2022-02-22 |
| 11227639 | Stacked DRAM device and method of manufacture | — | 2022-01-18 |
| 11114150 | Memory system with multiple open rows per bank | John Eric Linstadt, Liji Gopalakrishnan | 2021-09-07 |
| 11109512 | Memory subsystem for a cryogenic digital system | Frederick A. Ware, John Eric Linstadt | 2021-08-31 |
| 11081176 | 2T-1R architecture for resistive RAM | Deepak C. Sekar, Wayne F. Ellis, Brent Haukness, Gary B. Bronner | 2021-08-03 |