Issued Patents All Time
Showing 151–175 of 243 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7574616 | Memory device having a power down exit register | Richard M. Barth, Craig E. Hampel, Frederick A. Ware, Todd Bystrom, Bradley A. May +1 more | 2009-08-11 |
| 7571330 | System and module including a memory device having a power down mode | Richard M. Barth, Craig E. Hampel, Frederick A. Ware, Todd Bystrom, Bradley A. May +1 more | 2009-08-04 |
| 7565479 | Memory with refresh cycle donation to accommodate low-retention-storage rows | Scott C. Best | 2009-07-21 |
| 7562271 | Memory system topologies including a buffer device and an integrated circuit memory device | Ian Shaeffer, Craig E. Hampel | 2009-07-14 |
| 7536494 | Expandable slave device system with buffered subsystems | Bruno W. Garlepp, Richard M. Barth, Kevin S. Donnelly, Craig E. Hampel, Jeffrey D. Mitchell +4 more | 2009-05-19 |
| 7529141 | Asynchronous, high-bandwidth memory component using calibrated timing elements | Frederick A. Ware, Craig E. Hampel, Donald C. Stark | 2009-05-05 |
| 7526597 | Buffered memory having a control bus and dedicated data lines | Richard E. Perego, Fred Ware | 2009-04-28 |
| 7523248 | System having a controller device, a buffer device and a plurality of memory devices | Richard E. Perego, Stefanos Sidiropoulos | 2009-04-21 |
| 7484064 | Method and apparatus for signaling between devices of a memory system | Frederick A. Ware, Richard E. Perego, Craig E. Hampel | 2009-01-27 |
| 7464225 | Memory module including a plurality of integrated circuit memory devices and a plurality of buffer devices in a matrix topology | — | 2008-12-09 |
| 7454555 | Apparatus and method including a memory device having multiple sets of memory banks with duplicated data emulating a fast access time, fixed latency memory device | Frederick A. Ware, Steven C. Woo, Richard E. Perego | 2008-11-18 |
| 7444577 | Memory device testing to support address-differentiated refresh rates | Scott C. Best | 2008-10-28 |
| 7404032 | Configurable width buffered module having switch elements | Fred Ware, Richard E. Perego | 2008-07-22 |
| 7398413 | Memory device signaling system and method with independent timing calibration for parallel signal paths | Craig E. Hampel, Richard E. Perego, Stefanos Sidiropoulos, Fredrick A. Ware | 2008-07-08 |
| 7368961 | Clock distribution network supporting low-power mode | Carl W. Werner | 2008-05-06 |
| 7363422 | Configurable width buffered module | Richard E. Perego, Fred Ware | 2008-04-22 |
| 7362626 | Asynchronous, high-bandwidth memory component using calibrated timing elements | Frederick A. Ware, Craig E. Hampel, Donald C. Stark | 2008-04-22 |
| 7356639 | Configurable width buffered module having a bypass circuit | Richard E. Perego, Fred Ware, Craig E. Hampel | 2008-04-08 |
| 7353357 | Apparatus and method for pipelined memory operations | Richard M. Barth, Mark A. Horowitz, Donald C. Stark, Craig E. Hampel, Frederick A. Ware +1 more | 2008-04-01 |
| 7349279 | Memory Device Having a Configurable Oscillator for Refresh Operation | Richard M. Barth, Paul G. Davis, Craig E. Hampel | 2008-03-25 |
| 7337294 | Method and apparatus for adjusting the performance of a synchronous memory system | Bruno W. Garlepp, Pak Shing Chau, Kevin S. Donnelly, Clemenz Portmann, Donald C. Stark +3 more | 2008-02-26 |
| 7330951 | Apparatus and method for pipelined memory operations | John B. Dillon, Mark A. Horowitz, Donald C. Stark, Craig E. Hampel, Frederick A. Ware +1 more | 2008-02-12 |
| 7320047 | System having a controller device, a buffer device and a plurality of memory devices | Richard E. Perego, Stefanos Sidiropoulos | 2008-01-15 |
| 7320082 | Power control system for synchronous memory device | Richard M. Barth, Craig E. Hampel, Donald C. Stark | 2008-01-15 |
| 7266634 | Configurable width buffered module having flyby elements | Fred Ware, Richard E. Perego | 2007-09-04 |