Issued Patents All Time
Showing 26–50 of 116 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7986584 | Memory device having multiple power modes | Ely Tsern, Richard M. Barth, Craig E. Hampel | 2011-07-26 |
| 7978802 | Method and apparatus for a mesochronous transmission system | Prasun K. Raha, Dean Liu, Pak Shing Chau | 2011-07-12 |
| 7913104 | Method and apparatus for receive channel data alignment with minimized latency variation | Warren E. Cory, Dean Liu, Clemenz Portmann | 2011-03-22 |
| 7830735 | Asynchronous, high-bandwidth memory component using calibrated timing elements | Frederick A. Ware, Ely Tsern, Craig E. Hampel | 2010-11-09 |
| 7793039 | Interface for a semiconductor memory device and method for controlling the interface | Richard M. Barth, Frederick A. Ware, Craig E. Hampel, Paul G. Davis, Abhijit M. Abhyankar +2 more | 2010-09-07 |
| 7663966 | Single-clock, strobeless signaling system | — | 2010-02-16 |
| 7626880 | Memory device having a read pipeline and a delay locked loop | Ely Tsern, Richard M. Barth, Craig E. Hampel | 2009-12-01 |
| 7535933 | Calibrated data communication system and method | Jared L. Zerbe, Kevin S. Donnelly, Stefanos Sidiropoulos, Mark A. Horowitz, Leung Yu +5 more | 2009-05-19 |
| 7529141 | Asynchronous, high-bandwidth memory component using calibrated timing elements | Frederick A. Ware, Ely Tsern, Craig E. Hampel | 2009-05-05 |
| 7496709 | Integrated circuit memory device having delayed write timing based on read response time | Richard M. Barth, Frederick A. Ware, Craig E. Hampel, Paul G. Davis, Abhijit M. Abhyankar +2 more | 2009-02-24 |
| 7397725 | Single-clock, strobeless signaling system | — | 2008-07-08 |
| 7362626 | Asynchronous, high-bandwidth memory component using calibrated timing elements | Frederick A. Ware, Ely Tsern, Craig E. Hampel | 2008-04-22 |
| 7360050 | Integrated circuit memory device having delayed write capability | Richard M. Barth, Frederick A. Ware, Craig E. Hampel, Paul G. Davis, Abhijit M. Abhyankar +2 more | 2008-04-15 |
| 7353357 | Apparatus and method for pipelined memory operations | Richard M. Barth, Ely Tsern, Mark A. Horowitz, Craig E. Hampel, Frederick A. Ware +1 more | 2008-04-01 |
| 7337294 | Method and apparatus for adjusting the performance of a synchronous memory system | Bruno W. Garlepp, Pak Shing Chau, Kevin S. Donnelly, Clemenz Portmann, Stefanos Sidiropoulos +3 more | 2008-02-26 |
| 7331006 | Multiple sweep point testing of circuit devices | Timothy Chang | 2008-02-12 |
| 7330951 | Apparatus and method for pipelined memory operations | John B. Dillon, Ely Tsern, Mark A. Horowitz, Craig E. Hampel, Frederick A. Ware +1 more | 2008-02-12 |
| 7330953 | Memory system having delayed write timing | Richard M. Barth, Frederick A. Ware, Craig E. Hampel, Paul G. Davis, Abhijit M. Abhyankar +2 more | 2008-02-12 |
| 7330952 | Integrated circuit memory device having delayed write timing based on read response time | Richard M. Barth, Frederick A. Ware, Craig E. Hampel, Paul G. Davis, Abhijit M. Abhyankar +2 more | 2008-02-12 |
| 7320082 | Power control system for synchronous memory device | Ely Tsern, Richard M. Barth, Craig E. Hampel | 2008-01-15 |
| 7308065 | Delay locked loop circuitry for clock delay adjustment | Kevin S. Donnelly, Pak Shing Chau, Mark A. Horowitz, Thomas H. Lee, Mark G. Johnson +7 more | 2007-12-11 |
| 7287119 | Integrated circuit memory device with delayed write command processing | Richard M. Barth, Frederick A. Ware, Craig E. Hampel, Paul G. Davis, Abhijit M. Abhyankar +2 more | 2007-10-23 |
| 7287109 | Method of controlling a memory device having a memory core | Richard M. Barth, Frederick A. Ware, John B. Dillon, Craig E. Hampel, Matthew Murdy Griffin | 2007-10-23 |
| 7197611 | Integrated circuit memory device having write latency function | Richard M. Barth, Frederick A. Ware, Craig E. Hampel, Paul G. Davis, Abhijit M. Abhyankar +2 more | 2007-03-27 |
| 7148699 | Technique for calibrating electronic devices | — | 2006-12-12 |