Issued Patents All Time
Showing 26–50 of 53 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6470429 | System for identifying memory requests as noncacheable or reduce cache coherence directory lookups and bus snoops | Phillip M. Jones | 2002-10-22 |
| 6363439 | System and method for point-to-point serial communication between a system interface device and a bus interface device in a computer system | John Battles, Paul B. Rawlins, Patrick L. Ferguson | 2002-03-26 |
| 6356972 | System and method for concurrently requesting input/output and memory address space while maintaining order of data sent and returned therefrom | Kenneth T. Chin, Clarence K. Coffee, Michael J. Collins, Jerome J. Johnson, Phillip M. Jones +1 more | 2002-03-12 |
| 6286083 | Computer system with adaptive memory arbitration scheme | Kenneth T. Chin, Jerome J. Johnson, Phillip M. Jones, Gary J. Piccirillo, Jeffrey C. Stevens +2 more | 2001-09-04 |
| 6279065 | Computer system with improved memory access | Kenneth T. Chin, Jerome J. Johnson, Phillip M. Jones, Gary J. Piccirillo, C. Kevin Coffee +1 more | 2001-08-21 |
| 6272580 | Apparatus and method for dynamically elevating a lower level bus master to an upper level bus master within a multi-level arbitration system | Jeff Stevens, Phillip M. Jones, Jeff W. Wolford, Peter Bow Kwong Lee | 2001-08-07 |
| 6249847 | Computer system with synchronous memory arbiter that permits asynchronous memory requests | Kenneth T. Chin, Phillip M. Jones, Gary J. Piccirillo, Michael J. Collins | 2001-06-19 |
| 6247102 | Computer system employing memory controller and bridge interface permitting concurrent operation | Kenneth T. Chin, Jerome J. Johnson, Phillip M. Jones, Gary J. Piccirillo, Jeffrey C. Stevens +3 more | 2001-06-12 |
| 6216190 | System and method for optimally deferring or retrying a cycle upon a processor bus that is destined for a peripheral bus | Kenneth T. Chin, Clarence K. Coffee, Michael J. Collins, Jerome J. Johnson, Phillip M. Jones +1 more | 2001-04-10 |
| 6209052 | System and method for suppressing processor cycles to memory until after a peripheral device write cycle is acknowledged by the memory arbiter | Kenneth T. Chin, Clarence K. Coffee, Michael J. Collins, Jerome J. Johnson, Phillip M. Jones +1 more | 2001-03-27 |
| 6202101 | System and method for concurrently requesting input/output and memory address space while maintaining order of data sent and returned therefrom | Kenneth T. Chin, Clarence K. Coffee, Michael J. Collins, Jerome J. Johnson, Phillip M. Jones +1 more | 2001-03-13 |
| 6199118 | System and method for aligning an initial cache line of data read from an input/output device by a central processing unit | Kenneth T. Chin, Clarence K. Coffee, Michael J. Collins, Jerome J. Johnson, Phillip M. Jones +1 more | 2001-03-06 |
| 6160562 | System and method for aligning an initial cache line of data read from local memory by an input/output device | Kenneth T. Chin, Clarence K. Coffee, Michael J. Collins, Jerome J. Johnson, Phillip M. Jones +1 more | 2000-12-12 |
| 6088517 | Interfacing direct memory access devices to a non-ISA bus | Christopher C. Wanner, Jeffrey C. Stevens, Dwight D. Riley, David J. Maguire, James R. Edwards | 2000-07-11 |
| 6078338 | Accelerated graphics port programmable memory access arbiter | Ronald T. Horan, Phillip M. Jones, Gregory N. Santos, Gary J. Piccirillo | 2000-06-20 |
| 5999198 | Graphics address remapping table entry feature flags for customizing the operation of memory pages associated with an accelerated graphics port device | Ronald T. Horan, Phillip M. Jones, Gregory N. Santos, Robert C. Elliott | 1999-12-07 |
| 5999743 | System and method for dynamically allocating accelerated graphics port memory space | Ronald T. Horan, Phillip M. Jones, Gregory N. Santos, Robert C. Elliot | 1999-12-07 |
| 5990914 | Generating an error signal when accessing an invalid memory page | Ronald T. Horan, Phillip M. Jones, Gregory N. Santos, Robert C. Elliott | 1999-11-23 |
| 5949436 | Accelerated graphics port multiple entry gart cache allocation system and method | Ronald T. Horan, Phillip M. Jones, Gregory N. Santos, Jerome J. Johnson, Michael J. Collins | 1999-09-07 |
| 5936640 | Accelerated graphics port memory mapped status and control registers | Ronald T. Horan, Phillip M. Jones, Gregory N. Santos, Robert C. Elliott | 1999-08-10 |
| 5923859 | Dual arbiters for arbitrating access to a first and second bus in a computer system having bus masters on each bus | Maria L. Melo | 1999-07-13 |
| 5914727 | Valid flag for disabling allocation of accelerated graphics port memory space | Ronald T. Horan, Phillip M. Jones, Gregory N. Santos, Robert C. Elliott | 1999-06-22 |
| 5905509 | Accelerated Graphics Port two level Gart cache having distributed first level caches | Phillip M. Jones, Kenneth T. Chin | 1999-05-18 |
| 5884095 | Direct memory access controller having programmable timing | Jeff W. Wolford | 1999-03-16 |
| 5774680 | Interfacing direct memory access devices to a non-ISA bus | Christopher C. Wanner, Jeffrey C. Stevens, Dwight D. Riley, David J. Maguire, James R. Edwards | 1998-06-30 |