Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Scalable event handling in multi-threaded processor cores

Scalable event handling in multi-threaded processor cores

US Patent 9886396 · Granted Feb 6, 2018

Estimated economic value: $17,987,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Performing snoop filter replacement based on history-augmented victimization pri2025
Mechanism for instruction fusion2025
Performing instruction fetch pipeline synchronization (IFPS) in processor-based 2025
Mitigation of return stack buffer side channel attacks in a processor2025
Optimized compute hardware for machine learning operations2025
System and method for SRAM less electronic device bootup using cache2025
Coprocessor operation bundling2025
Coprocessors with bypass optimization, variable grid architecture, and fused vec2024
Instruction set architecture (ISA) format for multiple instruction set architect2024
Coprocessors with bypass optimization, variable grid architecture, and fused vec2024
Streaming engine for machine learning architecture2024
Method and apparatus for performing machine learning operations in parallel on m2024