Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Top level hierarchy wiring via 1×N compiler

Top level hierarchy wiring via 1×N compiler

US Patent 7966598 · Granted Jun 21, 2011

Estimated economic value: $7,220,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Systems and methods for associating vessels with user accounts2025
Power efficient voltage level translator circuit2022
Integrated circuit (IC) design methods using engineering change order (ECO) cell2020
Providing efficient handling of memory array failures in processor-based systems2020
Power distribution networks (PDNs) using hybrid grid and pillar arrangements2019
Standard cell architecture for diffusion based on fin count2019
Standard cell architecture for diffusion based on fin count2019
Mitigating length-of-diffusion effect for logic cells and placement thereof2019
Mitigating length-of-diffusion effect for logic cells and placement thereof2019
Standard cell architecture for diffusion based on fin count2019
Standard cell architecture for diffusion based on fin count2019
Complementary metal oxide semiconductor (CMOS) standard cell circuits employing 2018