{"@context": "https://schema.org", "@type": "BreadcrumbList", "itemListElement": [{"@type": "ListItem", "position": 1, "name": "Home", "item": "https://www.patentleaderboard.com/"}, {"@type": "ListItem", "position": 2, "name": "Method of fabricating a planar structure charge trapping memory cell array with rectangular gates and reduced bit line resistance", "item": "https://www.patentleaderboard.com/patent/6855608"}]}
Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Method of fabricating a planar structure charge trapping memory cell array with rectangular gates and reduced bit line resistance

Method of fabricating a planar structure charge trapping memory cell array with rectangular gates and reduced bit line resistance

US Patent 6855608 · Granted Feb 15, 2005

Estimated economic value: $5,967,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

X-ray imaging apparatus and positional deviation detection unit for X-ray imagin2025
Door handle2025
Three-dimensional nor array and method of making the same2025
Three-dimensional nor array and method of making the same2025
Numerical controller, numerical control machine tool, machining program generati2025
Voltage contrast metrology mark2024
Silicon carbide single crystal and semiconductor apparatus2024
Method to predict yield of a device manufacturing process2024
Method of manufacturing devices2024
Method for controlling a manufacturing process and associated apparatuses2024
Method for determining root cause affecting yield in a semiconductor manufacturi2023
X-ray imaging system and x-ray imaging apparatus2023