Issued Patents All Time
Showing 26–50 of 53 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8055872 | Data processor with hardware accelerator, accelerator interface and shared memory management unit | Nigel C. Paver, Chander Sudanthi | 2011-11-08 |
| 8041930 | Data processing apparatus and method for controlling thread access of register sets when selectively operating in secure and non-secure domains | David Hennah Mansell, David Michael Gilday, Daniel Kershaw | 2011-10-18 |
| 8041897 | Cache management within a data processing apparatus | Richard Roy Grisenthwaite, David Hennah Mansell | 2011-10-18 |
| 8001331 | Efficiency of cache memory operations | Nigel C. Paver, Chander Sudanthi, Timothy Charles Mace | 2011-08-16 |
| 7966466 | Memory domain based security control with data processing systems | Daniel Kershaw, Richard Roy Grisenthwaite | 2011-06-21 |
| 7937535 | Managing cache coherency in a data processing apparatus | Emre Ozer, Simon Andrew Ford | 2011-05-03 |
| 7886098 | Memory access security management | Daniel Kershaw | 2011-02-08 |
| 7877587 | Branch prediction within a multithreaded processor | Vladimir Vasekin, Yuri Levdik, Andrei Kapustin | 2011-01-25 |
| 7865675 | Controlling cleaning of data values within a hardware accelerator | Nigel C. Paver | 2011-01-04 |
| 7831817 | Two-level branch prediction apparatus | — | 2010-11-09 |
| 7805595 | Data processing apparatus and method for updating prediction data based on an operation's priority level | Emre Ozer, Alastair David Reid | 2010-09-28 |
| 7769955 | Multiple thread instruction fetch from different cache levels | Emre Ozer | 2010-08-03 |
| 7757027 | Control of master/slave communication within an integrated circuit | Christopher William Laycock, Antony John Harris, Bruce James Mathewson, Richard Roy Grisenthwaite | 2010-07-13 |
| 7743238 | Accessing items of architectural state from a register cache in a data processing apparatus when performing branch prediction operations for an indirect branch instruction | — | 2010-06-22 |
| 7707390 | Instruction issue control within a multi-threaded in-order superscalar processor | Emre Ozer, Vladimir Vasekin | 2010-04-27 |
| 7685404 | Program subgraph identification | Krisztian Flautner, Scott Mahlke, Nathan Clark | 2010-03-23 |
| 7657694 | Handling access requests in a data processing apparatus | David Hennah Mansell, Stephen John Hill | 2010-02-02 |
| 7650483 | Execution of instructions within a data processing apparatus having a plurality of processing units | Elodie Charra, Frederic Claude Marie Piry, Richard Roy Grisenthwaite, Melanie Emanuelle Lucie Vincent, Norbert Bernard Eugene Lataille +1 more | 2010-01-19 |
| 7529889 | Data processing apparatus and method for performing a cache lookup in an energy efficient manner | Vladimir Vasekin | 2009-05-05 |
| 7506091 | Interrupt controller utilising programmable priority values | Daniel Kershaw, Richard Roy Grisenthwaite, David Hennah Mansell | 2009-03-17 |
| 7447883 | Allocation of branch target cache resources in dependence upon program instructions within an instruction queue | Vladimir Vasekin, Andrew Christopher Rose, Wilco Dijkstra | 2008-11-04 |
| 7350055 | Tightly coupled accelerator | Krisztian Flautner, Scott Mahlke, Nathan Clark | 2008-03-25 |
| 7343482 | Program subgraph identification | Krisztian Flautner, Scott Mahlke, Nathan Clark | 2008-03-11 |
| 7318143 | Reuseable configuration data | Krisztian Flautner, Scott Mahlke, Nathan Clark | 2008-01-08 |
| 7269759 | Data processing apparatus and method for handling corrupted data values | — | 2007-09-11 |