NL

Norbert Bernard Eugene Lataille

NV NVIDIA: 11 patents #639 of 7,811Top 9%
AS Amadeus S.A.S.: 2 patents #112 of 642Top 20%
Overall (All Time): #378,114 of 4,157,543Top 10%
13
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
10657449 System and method for load distribution in a network Alexandre Sbragia, Renaud Arnoux-Prost, Eric Bousquet, David Renaudie 2020-05-19
9031891 Computing system and method for controlling the execution of a decision process to maintain the data access efficiency upon receipt of an availability information inquiry Renaud Arnoux-Prost, Alexandre Sbragia, Eric Bousquet, David Renaudie 2015-05-12
8769251 Data processing apparatus and method for converting data values between endian formats Philippe Luc, Florent Begon, Nicolas Chaussade 2014-07-01
8271730 Handling of write access requests to shared memory in a data processing apparatus Frederic Claude Marie Piry, Philippe Jean-Pierre Raphalen, Stuart David Biles, Richard Roy Grisenthwaite 2012-09-18
7925868 Suppressing register renaming for conditional instructions predicted as not executed Florent Begon, Cedric Denis Robert Airaud, Melanie Emanuelle Lucie Vincent 2011-04-12
7856532 Cache logic, data processing apparatus including cache logic, and a method of operating cache logic Cedric Denis Robert Airaud, Philippe Jean-Pierre Raphalen 2010-12-21
7844800 Method for renaming a large number of registers in a data processing system using a background channel Melanie Emanuelle Lucie Vincent, Florent Begon, Cedric Denis Robert Airaud 2010-11-30
7809930 Selective suppression of register renaming Frederic Claude Marie Piry 2010-10-05
7698537 Data processing apparatus for processing a stream of instructions in first and second processing blocks with the first processing block supporting register renaming and the second processing block not supporting register renaming Cedric Denis Robert Airaud, Melanie Emanuelle Lucie Vincent, Luc Orion 2010-04-13
7650483 Execution of instructions within a data processing apparatus having a plurality of processing units Elodie Charra, Frederic Claude Marie Piry, Richard Roy Grisenthwaite, Melanie Emanuelle Lucie Vincent, Jocelyn Francois Orion Jaubert +1 more 2010-01-19
7624253 Determining register availability for register renaming Florent Begon, Cedric Denis Robert Airaud, Melanie Emanuelle Lucie Vincent 2009-11-24
7590826 Speculative data value usage Florent Begon, Philippe Jean-Pierre Raphalen, Frederic Claude Marie Piry 2009-09-15
7162590 Memory bus within a coherent multi-processing system having a main portion and a coherent multi-processing portion Julie-Anne Pruvost, Stuart David Biles 2007-01-09