Issued Patents All Time
Showing 26–50 of 56 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8237705 | Hierarchical processor array | John Erik Lindholm, John S. Montrym, Emmett M. Kilgariff, Simon Moy, Brett W. Coon +2 more | 2012-08-07 |
| 8077174 | Hierarchical processor array | John Erik Lindholm, John S. Montrym, Emmett M. Kilgariff, Simon Moy, Brett W. Coon +2 more | 2011-12-13 |
| 8060765 | Power estimation based on block activity | Hungse Cha, Robert J. Hasslen, III, John A. Robinson, Abdulkadir Utku Diril | 2011-11-15 |
| 8041841 | Protocol and interface for source-synchronous digital link | Edward Liu | 2011-10-18 |
| 7966439 | Apparatus, system, and method for a fast data return memory controller | Brad W. Simeral, Roman Surgutchick, Anand Srinivasan, Dmitry Vyshetsky | 2011-06-21 |
| 7958483 | Clock throttling based on activity-level signals | Jonah M. Alben, Robert J. Hasslen, III | 2011-06-07 |
| 7852340 | Scalable shader architecture | Rui M. Bastos, Karim M. Abdalla, Christian Rouet, Michael J. M. Toksvig, Johnny S. Rhoades +6 more | 2010-12-14 |
| 7836318 | Memory clock slowdown | Jonah M. Alben, Adam E. Levinthal | 2010-11-16 |
| 7821520 | Fragment processor having dual mode register file | Rui M. Bastos, Karim M. Abdalla, Emmett M. Kilgariff | 2010-10-26 |
| 7809782 | Method and system for selecting a set of parameters | Nicholas J. Foskett, Robert J. Prevett, Jr. | 2010-10-05 |
| 7747915 | System and method for improving the yield of integrated circuits containing memory | Anthony Michael Tamasi, Oren Rubenstein, Srihari Raju Vegesna, Jue Wu | 2010-06-29 |
| 7746349 | Method and apparatus for display of data | Krishnaraj S. Rao, David G. Reed | 2010-06-29 |
| 7584321 | Memory address and datapath multiplexing | Chris Malachowsky, David G. Reed, Brad W. Simeral | 2009-09-01 |
| 7562205 | Virtual address translation system with caching of variable-range translation clusters | Colyn S. Case, Dmitry Vyshetsky | 2009-07-14 |
| 7523209 | Protocol and interface for source-synchronous digital link | Edward Liu | 2009-04-21 |
| 7478289 | System and method for improving the yield of integrated circuits containing memory | Anthony Michael Tamasi, Oren Rubenstein, Srihari Raju Vegesna, Jue Wu | 2009-01-13 |
| 7406546 | Long-distance synchronous bus | Blaise A. Vignon | 2008-07-29 |
| 7385607 | Scalable shader architecture | Rui M. Bastos, Karim M. Abdalla, Christian Rouet, Michael J. M. Toksvig, Johnny S. Rhoades +6 more | 2008-06-10 |
| 7334108 | Multi-client virtual address translation system with translation units of variable-range size | Colyn S. Case, Dmitry Vyshetsky | 2008-02-19 |
| 7287145 | System, apparatus and method for reclaiming memory holes in memory composed of identically-sized memory devices | Brad W. Simeral, David G. Reed, Roman Surgutchik | 2007-10-23 |
| 7278008 | Virtual address translation system with caching of variable-range translation clusters | Colyn S. Case, Dmitry Vyshetsky | 2007-10-02 |
| 7275143 | System, apparatus and method for avoiding page conflicts by characterizing addresses in parallel with translations of memory addresses | Brad W. Simeral, David G. Reed | 2007-09-25 |
| 7240179 | System, apparatus and method for reclaiming memory holes in memory composed of arbitrarily-sized memory devices | Brad W. Simeral, David G. Reed, Roman Surgutchik | 2007-07-03 |
| 7187220 | Memory clock slowdown | Jonah M. Alben, Adam E. Levinthal | 2007-03-06 |
| 7117238 | Method and system for performing pipelined reciprocal and reciprocal square root operations | Nicholas J. Foskett, Robert J. Prevett, Jr. | 2006-10-03 |