Issued Patents All Time
Showing 51–75 of 86 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9606808 | Method and system for resolving thread divergences | Xiaogang Qiu, Jeff Tuckey, Michael Siu, Robert J. Stoll, Olivier Giroux | 2017-03-28 |
| 9477482 | System, method, and computer program product for implementing multi-cycle register file bypass | Xiaogang Qiu, Ian Kwong, Ming Y. Siu, Michael A. Fetterman | 2016-10-25 |
| 9477480 | System and processor for implementing interruptible batches of instructions | Olivier Giroux, Robert Ohannessian, Michael A. Fetterman | 2016-10-25 |
| 9471307 | System and processor that include an implementation of decoupled pipelines | Olivier Giroux, Michael A. Fetterman, Robert Ohannessian, Shirish Gadre, Xiaogang Qiu +2 more | 2016-10-18 |
| 9430242 | Throttling instruction issue rate based on updated moving average to avoid surges in DI/DT | Peter Nelson, Olivier Giroux | 2016-08-30 |
| 9361114 | Instruction based interrupt masking for managing interrupts in a computer environment | Gil Tene, Scott D. Sellers, Michael A. Wolf | 2016-06-07 |
| 9336005 | Cooperative preemption | Gil Tene, Michael A. Wolf, Scott D. Sellers | 2016-05-10 |
| 9110810 | Multi-level instruction cache prefetching | Nicholas Wang | 2015-08-18 |
| 8949841 | Approach for a configurable phase-based priority scheduler | Olivier Giroux, Robert J. Stoll, Gary M. Tarolli, John Erik Lindholm | 2015-02-03 |
| 8732713 | Thread group scheduler for computing on a parallel thread processor | Brett W. Coon, John R. Nickolls, John Erik Lindholm, Robert J. Stoll, Nicholas Wang | 2014-05-20 |
| 8639882 | Methods and apparatus for source operand collector caching | Manuel Gautho, John Erik Lindholm | 2014-01-28 |
| 8544020 | Cooperative preemption | Gil Tene, Michael A. Wolf, Scott D. Sellers | 2013-09-24 |
| 8522000 | Trap handler architecture for a parallel processing unit | Michael C. Shebanow, Brett W. Coon, Steven James Heinrich, Aravind Kalaiah, John R. Nickolls +4 more | 2013-08-27 |
| 8230271 | Detecting software race conditions | Daniel D. Grove, Ivan Posva, Cliff N. Click, Jr., Jeffrey Gee | 2012-07-24 |
| 8108628 | Processor instruction used to perform a matrix test to generate a memory-related trap | Gil Tene, Michael A. Wolf | 2012-01-31 |
| 7844862 | Detecting software race conditions | Daniel D. Grove, Ivan Posva, Cliff N. Click, Jr., Jeffrey Gee | 2010-11-30 |
| 7689782 | Processor instruction used to determine whether to perform a memory-related trap | Gil Tene, Michael A. Wolf | 2010-03-30 |
| 7577801 | Array access | Gil Tene, Scott D. Sellers, Cliff N. Click, Jr. | 2009-08-18 |
| 7552302 | Ordering operation | Gil Tene, Kevin Normoyle, David Kruckernyer, Cliff N. Click, Jr. | 2009-06-23 |
| 7437597 | Write-back cache with different ECC codings for clean and dirty lines with refetching of uncorrectable clean lines | David A. Kruckemyer, Kevin Normoyle | 2008-10-14 |
| 7376800 | Speculative multiaddress atomicity | Gil Tene, Kevin Normoyle | 2008-05-20 |
| 7337339 | Multi-level power monitoring, filtering and throttling at local blocks and globally | Kevin Normoyle, Elias M. ATMEH, Scott D. Sellers, Murali Sundaresan, Manuel Gautho | 2008-02-26 |
| 7225300 | Duplicate snoop tags partitioned across multiple processor/cache chips in a multi-processor system | David A. Kruckemyer, Robert Hathaway | 2007-05-29 |
| 7188232 | Pipelined processing with commit speculation staging buffer and load/store centric exception handling | — | 2007-03-06 |
| 7062767 | Method for coordinating information flow between components | Dominic Paul McCarthy | 2006-06-13 |