Issued Patents All Time
Showing 51–75 of 104 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7575948 | Method for operating photosensitive device | Ya-Chin King | 2009-08-18 |
| 7551494 | Single-poly non-volatile memory device and its operation method | Hsin-Ming Chen, Shih-Jye Shen, Ya-Chin King, Ching-Hsiang Hsu | 2009-06-23 |
| 7122857 | Multi-level (4state/2-bit) stacked gate flash memory cell | Shui-Hung Chen, Hsin-Ming Chen | 2006-10-17 |
| 7057228 | Memory array with byte-alterable capability | Yue-Der Chih, Sheng-Wei Tsao, Chin-Huang Wang | 2006-06-06 |
| 6982458 | Method of making the selection gate in a split-gate flash EEPROM cell and its structure | Wen-Ting Chu, Jack Y. Yeh | 2006-01-03 |
| 6933198 | Method for forming enhanced areal density split gate field effect transistor device array | Wen-Ting Chu, Chia-Ta Hsieh | 2005-08-23 |
| 6902978 | Method of making the selection gate in a split-gate flash EEPROM cell and its structure | Wen-Ting Chu, Jack Y. Yeh | 2005-06-07 |
| 6838725 | Step-shaped floating poly-si gate to improve a gate coupling ratio for flash memory application | Shui-Hung Chen | 2005-01-04 |
| 6787418 | Method of making the selection gate in a split-gate flash eeprom cell and its structure | Wen-Ting Chu, Jack Y. Yeh | 2004-09-07 |
| 6734055 | Multi-level (4 state/2-bit) stacked gate flash memory cell | Shui-Hung Chen, Hsin-Ming Chen | 2004-05-11 |
| 6724036 | Stacked-gate flash memory cell with folding gate and increased coupling ratio | Chia-Ta Hsieh, Di-Son Kuo, Yai-Fen Lin, Jong Chen, Hung-Der Su | 2004-04-20 |
| 6586765 | Wafer-level antenna effect detection pattern for VLSI | Hsin-Ming Chen | 2003-07-01 |
| 6583466 | Vertical split gate flash memory device in an orthogonal array of rows and columns with devices in columns having shared source regions | Shui-Hung Chen, Di-Son Kuo | 2003-06-24 |
| 6576558 | High aspect ratio shallow trench using silicon implanted oxide | Hsin-Ming Chen | 2003-06-10 |
| 6548856 | Vertical stacked gate flash memory device | Shui-Hung Chen, Mong-Song Liang | 2003-04-15 |
| 6544828 | Adding a poly-strip on isolation's edge to improve endurance of high voltage NMOS on EEPROM | Wen-Ting Chu, Di-Son Kuo, Jack Y. Yeh, Chia-Ta Hsieh, Sheng-Wei Tsaur | 2003-04-08 |
| 6495880 | Method to fabricate a flash memory cell with a planar stacked gate | Jong Chen, Hung-Der Su, Di-Son Kuo | 2002-12-17 |
| 6465836 | Vertical split gate field effect transistor (FET) device | Sheng-Wei Tsao, Di-Son Kuo, Jack Y. Yeh, Wen-Ting Chu, Chung-Li Chang +1 more | 2002-10-15 |
| 6437408 | Plasma damage protection cell using floating N/P/N and P/N/P structure | Jiaw-Ren Shih, Shui Shen, Jian-Hsing Lee | 2002-08-20 |
| 6437397 | Flash memory cell with vertically oriented channel | Shui-Hung Chen, Jong Chen, Di-Son Kuo | 2002-08-20 |
| 6420233 | Split gate field effect transistor (FET) device employing non-linear polysilicon floating gate electrode dopant profile | Chia-Ta Hsieh, Di-Son Kuo, Jake Yeh, Chung-Li Chang, Wen-Ting Chu | 2002-07-16 |
| 6391719 | Method of manufacture of vertical split gate flash memory device | Shui-Hung Chen, Di-Son Kuo | 2002-05-21 |
| 6372525 | Wafer-level antenna effect detection pattern for VLSI | Hsin-Ming Chen | 2002-04-16 |
| 6348382 | Integration process to increase high voltage breakdown performance | Hung-Der Su, Jong Chen, Wen-Ting Chu | 2002-02-19 |
| 6326662 | Split gate flash memory device with source line | Chia-Ta Hsieh, Shui-Hung Chen, Di-Son Kuo | 2001-12-04 |