Issued Patents All Time
Showing 76–100 of 104 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6297099 | Method to free control tunneling oxide thickness on poly tip of flash | Chia-Ta Hsieh, Di-Son Kuo, Jack Y. Yeh, Wen-Ting Chu, Chung-Li Chang | 2001-10-02 |
| 6297098 | Tilt-angle ion implant to improve junction breakdown in flash memory application | Hung-Der Su, Jong Chen, Wen-Ting Chu | 2001-10-02 |
| 6277723 | Plasma damage protection cell using floating N/P/N and P/N/P structure | Jiaw-Ren Shih, Shui-Hung Chen, Jian-Hsing Lee | 2001-08-21 |
| 6251744 | Implant method to improve characteristics of high voltage isolation and high voltage breakdown | Hung-Der Su, Jong Chen, Wen-Ting Chu, Hung-Cheng Sung, Di-Son Kuo | 2001-06-26 |
| 6242314 | Method for fabricating a on-chip temperature controller by co-implant polysilicon resistor | Shui-Hung Chen, Jiaw-Ren Shih | 2001-06-05 |
| 6225162 | Step-shaped floating poly-si gate to improve gate coupling ratio for flash memory application | Shui-Hung Chen | 2001-05-01 |
| 6207532 | STI process for improving isolation for deep sub-micron application | Shui-Hung Chen, Jiaw-Ren Shih | 2001-03-27 |
| 6190969 | Method to fabricate a flash memory cell with a planar stacked gate | Jong Chen, Hung-Der Su, Di-Son Kuo | 2001-02-20 |
| 6172395 | Method of manufacture of self-aligned floating gate, flash memory cell and device manufactured thereby | Jong Chen | 2001-01-09 |
| 6153494 | Method to increase the coupling ratio of word line to floating gate by lateral coupling in stacked-gate flash | Chia-Ta Hsieh, Di-Son Kuo, Yai-Fen Lin, Jong Chen, Hung-Der Su | 2000-11-28 |
| 6133096 | Process for simultaneously fabricating a stack gate flash memory cell and salicided periphereral devices | Hung-Der Su, Jong Chen, Di-Son Kuo | 2000-10-17 |
| 6133097 | Method for forming mirror image split gate flash memory devices by forming a central source line slot | Chia-Ta Hsieh, Shui-Hung Chen, Di-Son Kuo | 2000-10-17 |
| 6130168 | Using ONO as hard mask to reduce STI oxide loss on low voltage device in flash or EPROM process | Wen-Ting Chu, Di-Son Kuo, Hung-Der Su, Jong Chen | 2000-10-10 |
| 6127227 | Thin ONO thickness control and gradual gate oxidation suppression by b. N.su2 treatment in flash memory | Jong Chen, Hung-Der Su, Di-Son Kuo | 2000-10-03 |
| 6127226 | Method for forming vertical channel flash memory cell using P/N junction isolation | Jong Chen, Shui-Hung Chen, Di-Son Kuo | 2000-10-03 |
| 6124177 | Method for making deep sub-micron mosfet structures having improved electrical characteristics | Hung-Der Su, Jong Chen, Wen-Ting Chu | 2000-09-26 |
| 6108242 | Flash memory with split gate structure and method of fabricating the same | Hsin-Ming Chen | 2000-08-22 |
| 6093606 | Method of manufacture of vertical stacked gate flash memory device | Shui-Hung Chen, Mong-Song Liang | 2000-07-25 |
| 6078076 | Vertical channels in split-gate flash memory cell | Chia-Ta Hsieh, Jong Chen, Di-Son Kuo | 2000-06-20 |
| 6074915 | Method of making embedded flash memory with salicide and sac structure | Jong Chen, Hung-Der Su, Di-Son Kuo | 2000-06-13 |
| 6066874 | Flash memory cell with vertical channels, and source/drain bus lines | Shui-Hung Chen, Jong Chen, Di-Son Kuo | 2000-05-23 |
| 6063664 | Method of making EEPROM with trenched structure | Jong Chen, Di-Son Kuo | 2000-05-16 |
| 6037223 | Stack gate flash memory cell featuring symmetric self aligned contact structures | Hung-Der Su, Jong Chen, Di-Son Kuo | 2000-03-14 |
| 6013551 | Method of manufacture of self-aligned floating gate, flash memory cell and device manufactured thereby | Jong Chen | 2000-01-11 |
| 6011288 | Flash memory cell with vertical channels, and source/drain bus lines | Shui-Hung Chen, Jong Chen, Di-Son Kuo | 2000-01-04 |