YC

Yong Poo Chia

Micron: 56 patents #309 of 6,345Top 5%
AI Aptina Imaging: 1 patents #187 of 332Top 60%
📍 Singapore, SG: #52 of 13,971 inventorsTop 1%
Overall (All Time): #41,658 of 4,157,543Top 2%
58
Patents All Time

Issued Patents All Time

Showing 26–50 of 58 patents

Patent #TitleCo-InventorsDate
8232657 Packaged semiconductor assemblies and methods for manufacturing such assemblies Suan Jeung Boon, Meow Koon Eng 2012-07-31
8198720 Microelectronic die packages with metal leads, including metal leads for stacked die packages, and associated systems and methods Meow Koon Eng, Suan Jeung Boon 2012-06-12
8106488 Wafer level packaging Swee Kwang Chua, Suan Jeung Boon, Neo Yong Loo 2012-01-31
8065792 Method for packaging circuits Low Siu Waf, Suan Jeung Boon, Eng Meow Koon, Swee Kwang Chua 2011-11-29
8063493 Semiconductor device assemblies and packages Suan Jeung Boon, Meow Koon Eng, Siu Waf Low 2011-11-22
7884007 Super high density module with integrated wafer level packages Suan Jeung Boon, Siu Waf Low, Yong Loo Neo, Bok Leng Ser 2011-02-08
7855462 Packaged semiconductor assemblies and methods for manufacturing such assemblies Suan Jeung Boon, Meow Koon Eng 2010-12-21
7843050 Microelectronic die packages with metal leads, including metal leads for stacked die packages, and associated systems and methods Meow Koon Eng, Suan Jeung Boon 2010-11-30
7820484 Wafer level packaging Swee Kwang Chua, Suan Jeung Boon, Yong Loo Neo 2010-10-26
7791203 Interconnects for packaged semiconductor devices and methods for manufacturing such devices Suan Jeung Boon, Meow Koon Eng 2010-09-07
7712211 Method for packaging circuits and packaged circuits Low Siu Waf, Suan Jeung Boon, Eng Meow Koon, Swee Kwang Chua 2010-05-11
7674655 Semiconductor assemblies and methods of manufacturing such assemblies including forming trenches in a first side of the molding material Swee Kwang Chua, Suan Jeung Boon 2010-03-09
7659134 Microelectronic imagers and methods for manufacturing such microelectronic imagers Yong Loo Neo, Meow Koon Eng 2010-02-09
7633159 Semiconductor device assemblies and packages with edge contacts and sacrificial substrates and other intermediate structures used or formed in fabricating the assemblies or packages Suan Jeung Boon, Meow Koon Eng, Siu Waf Low 2009-12-15
7579681 Super high density module with integrated wafer level packages Suan Jeung Boon, Siu Waf Low, Yong Loo Neo, Bok Leng Ser 2009-08-25
7553697 Multiple chip semiconductor package Meow Koon Eng, Yong Loo Neo, Suan Jeung Boon, Siu Waf Low, Swee Kwang Chua +1 more 2009-06-30
7485562 Method of making multichip wafer level packages and computing systems incorporating same Swee Kwang Chua, Siu Waf Low, Meow Koon Eng, Yong Loo Neo, Suan Jeung Boon +2 more 2009-02-03
7375009 Method of forming a conductive via through a wafer Swee Kwang Chua, Suan Jeung Boon, Yong Loo Neo 2008-05-20
7368374 Super high density module with integrated wafer level packages Suan Jeung Boon, Siu Waf Low, Yong Loo Neo, Bok Leng Ser 2008-05-06
7304375 Castellation wafer level packaging of integrated circuit chips Suan Jeung Boon, Siu Waf Low, Meow Koon Eng, Swee Kwang Chua, Shuang Wu Huang +2 more 2007-12-04
7274094 Leadless packaging for image sensor devices Suan Jeung Boon, Yong Loo Neo, Swee Kwang Chua, Siu Waf Low 2007-09-25
7271027 Castellation wafer level packaging of integrated circuit chips Suan Jeung Boon, Siu Waf Low, Meow Koon Eng, Swee Chua, Shuang Wu Huang +2 more 2007-09-18
7208335 Castellated chip-scale packages and methods for fabricating the same Suan Jeung Boon, Meow Koon Eng, Siu Waf Low 2007-04-24
7193312 Castellation wafer level packaging of integrated circuit chips Suan Jeung Boon, Siu Waf Low, Meow Koon Eng, Swee Kwang Chua, Shuang Wu Huang +2 more 2007-03-20
7173330 Multiple chip semiconductor package Meow Koon Eng, Yong Loo Neo, Suan Jeung Boon, Siu Waf Low, Swee Kwang Chua +1 more 2007-02-06