Issued Patents All Time
Showing 101–117 of 117 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6831854 | Cross point memory array using distinct voltages | Darrell Rinerson, Steven W. Longcor, Christophe J. Chevallier, Edmond R. Ward, Steve Kuo-Ren Hsia | 2004-12-14 |
| 6753561 | Cross point memory array using multiple thin films | Darrell Rinerson, Steven W. Longcor, Edmond R. Ward, Steve Kuo-Ren Hsia, Christophe J. Chevallier | 2004-06-22 |
| 5995408 | Nonvolatile ferroelectric memory with folded bit line architecture | — | 1999-11-30 |
| 5985714 | Method of forming a capacitor | Gurtej S. Sandhu, Paul J. Schuele | 1999-11-16 |
| 5955758 | Method of forming a capacitor plate and a capacitor incorporating same | Gurtej S. Sandhu, Paul J. Schuele | 1999-09-21 |
| 5852571 | Nonvolatile ferroelectric memory with folded bit line architecture | — | 1998-12-22 |
| 5654222 | Method for forming a capacitor with electrically interconnected construction | Gurtej S. Sandhu, Paul J. Schuele | 1997-08-05 |
| 5541872 | Folded bit line ferroelectric memory device | Tyler Lowrey | 1996-07-30 |
| 5536672 | Fabrication of ferroelectric capacitor and memory cell | William D. Miller, Joseph T. Evans, Jr., William H. Shepherd | 1996-07-16 |
| 5424975 | Reference circuit for a non-volatile ferroelectric memory | Tyler Lowrey | 1995-06-13 |
| 5357463 | Method for reverse programming of a flash EEPROM | — | 1994-10-18 |
| 5345104 | Flash memory cell having antimony drain for reduced drain voltage during programming | Kirk D. Prall | 1994-09-06 |
| 5179038 | High density trench isolation for MOS circuits | John P. Niemi, Jonathan E. Macro, David Back | 1993-01-12 |
| 5046043 | Ferroelectric capacitor and memory cell including barrier and isolation layers | William D. Miller, Joseph T. Evans, Jr., William H. Shepherd | 1991-09-03 |
| 4649627 | Method of fabricating silicon-on-insulator transistors with a shared element | John R. Abernathey, Jerome B. Lasky, Scott R. Stiffler | 1987-03-17 |
| 4558508 | Process of making dual well CMOS semiconductor structure with aligned field-dopings using single masking step | Charles W. Koburger, III, Jerome B. Lasky, Larry A. Nesbit, Ronald R. Troutman, Francis R. White | 1985-12-17 |
| 4532700 | Method of manufacturing semiconductor structures having an oxidized porous silicon isolation layer | Jerome B. Lasky, Larry A. Nesbit | 1985-08-06 |