Issued Patents All Time
Showing 51–75 of 88 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6225208 | Method and structure for improved alignment tolerance in multiple, singularized plugs | — | 2001-05-01 |
| 6180452 | Shared length cell for improved capacitance | — | 2001-01-30 |
| 6146961 | Processing methods of forming a capacitor | Thomas M. Graettinger, Paul J. Schuele, Pierre C. Fazan, Li Li, Zhiqiang Wu +1 more | 2000-11-14 |
| 6143620 | Semiconductor processing method of providing a roughened polysilicon film and a capacitor construction | Sujit Sharan | 2000-11-07 |
| 6117764 | Use of a plasma source to form a layer during the formation of a semiconductor device | Kevin G. Donohoe, Thomas J. Dunbar | 2000-09-12 |
| 6100156 | Method for forming a contact intermediate two adjacent electrical components | Pai-Hung Pan | 2000-08-08 |
| 6066552 | Method and structure for improved alignment tolerance in multiple, singularized plugs | — | 2000-05-23 |
| 6048763 | Integrated capacitor bottom electrode with etch stop layer | Trung T. Doan | 2000-04-11 |
| 6049101 | Processing methods of forming a capacitor, and capacitor construction | Thomas M. Graettinger, Paul J. Schuele, Pierre C. Fazan, Li Li, Zhiqiang Wu +1 more | 2000-04-11 |
| 6027970 | Method of increasing capacitance of memory cells incorporating hemispherical grained silicon | Sujit Sharan, Anand Srinivasan, Gurtej S. Sandhu | 2000-02-22 |
| 6025624 | Shared length cell for improved capacitance | — | 2000-02-15 |
| 5985732 | Method of forming integrated stacked capacitors with rounded corners | Pierre C. Fazan, Klaus Schuegraf | 1999-11-16 |
| 5972771 | Enhancing semiconductor structure surface area using HSG and etching | — | 1999-10-26 |
| 5963804 | Method of making a doped silicon structure with impression image on opposing roughened surfaces | Zhiquiang Wu, Li Li | 1999-10-05 |
| 5950092 | Use of a plasma source to form a layer during the formation of a semiconductor device | Kevin G. Donohoe, Thomas J. Dunbar | 1999-09-07 |
| 5933727 | Method for increasing capacitance of an HSG rugged capacitor using a phosphine rich oxidation and subsequent wet etch | — | 1999-08-03 |
| 5891768 | Method of forming a capacitor | Pierre C. Fazan | 1999-04-06 |
| 5888881 | Method of trench isolation during the formation of a semiconductor device | Nanseng Jeng | 1999-03-30 |
| 5889300 | Capacitor with containers members | Pierre C. Fazan | 1999-03-30 |
| 5872033 | Method for increasing capacitance of an HSG rugged capacitor using a phosphine rich oxidation and subsequent wet etch | — | 1999-02-16 |
| 5856007 | Method and apparatus for forming features in holes, trenches and other voids in the manufacturing of microelectronic devices | Sujit Sharan | 1999-01-05 |
| 5849624 | Method of fabricating a bottom electrode with rounded corners for an integrated memory cell capacitor | Pierre C. Fazan, Klaus Schuegraf | 1998-12-15 |
| 5837596 | Field oxide formation by oxidation of polysilicon layer | Nanseng Jeng | 1998-11-17 |
| 5837378 | Method of reducing stress-induced defects in silicon | Viju K. Mathews, Nanseng Jeng, Pierre C. Fazan | 1998-11-17 |
| 5830793 | Method of selective texfturing for patterned polysilicon electrodes | Klaus Schuegraf, Pierre C. Fazan | 1998-11-03 |