Issued Patents All Time
Showing 176–198 of 198 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5977636 | Method of forming an electrically conductive contact plug, method of forming a reactive or diffusion barrier layer over a substrate, integrated circuitry, and method of forming a layer of titanium boride | — | 1999-11-02 |
| 5976976 | Method of forming titanium silicide and titanium by chemical vapor deposition | Trung T. Doan, Gurtej S. Sandhu, Kirk D. Prall | 1999-11-02 |
| 5963832 | Removal of metal cusp for improved contact fill | Anand Srinivasan, Gurtej S. Sandhu | 1999-10-05 |
| 5946594 | Chemical vapor deposition of titanium from titanium tetrachloride and hydrocarbon reactants | Ravi Iyer | 1999-08-31 |
| 5935336 | Apparatus to increase gas residence time in a reactor | Gurtej S. Sandhu, Ravi Iyer | 1999-08-10 |
| 5929526 | Removal of metal cusp for improved contact fill | Anand Srinivasan, Gurtej S. Sandhu | 1999-07-27 |
| 5882978 | Methods of forming a silicon nitride film, a capacitor dielectric layer and a capacitor | Anand Srinivasan, Gurtej S. Sandhu | 1999-03-16 |
| 5861344 | Facet etch for improved step coverage of integrated circuit contacts | Ceredig Roberts, Anand Srinivasan, Gurtej S. Sandhu | 1999-01-19 |
| 5856007 | Method and apparatus for forming features in holes, trenches and other voids in the manufacturing of microelectronic devices | Thomas A. Figura | 1999-01-05 |
| 5846881 | Low cost DRAM metallization | Gurtej S. Sandhu | 1998-12-08 |
| 5831334 | Field effect transistors comprising electrically conductive plugs having monocrystalline and polycrystalline silicon | Kirk D. Prall, Pai-Hung Pan | 1998-11-03 |
| 5759905 | Semiconductor processing method of forming a conductively doped semiconductive material plug within a contact opening | Pai-Hung Pan, Kirk D. Prall | 1998-06-02 |
| 5750012 | Multiple species sputtering for improved bottom coverage and improved sputter rate | P. J. Ireland, Howard E. Rhodes, Sukesh Sandhu, Tim O'Brien, Tim Johnson | 1998-05-12 |
| 5747116 | Method of forming an electrical contact to a silicon substrate | Gurtej S. Sandhu | 1998-05-05 |
| 5735960 | Apparatus and method to increase gas residence time in a reactor | Gurtej S. Sandhu, Ravi Iyer | 1998-04-07 |
| 5730835 | Facet etch for improved step coverage of integrated circuit contacts | Ceredig Roberts, Anand Srinivasan, Gurtej S. Sandhu | 1998-03-24 |
| 5731235 | Methods of forming a silicon nitrite film, a capacitor dielectric layer and a capacitor | Anand Srinivasan, Gurtej S. Sandhu | 1998-03-24 |
| 5700716 | Method for forming low contact resistance contacts, vias, and plugs with diffusion barriers | Varatharajan Nagabushnam | 1997-12-23 |
| 5677573 | Field effect transistor | Kirk D. Prall, Pai-Hung Pan | 1997-10-14 |
| 5664988 | Process of polishing a semiconductor wafer having an orientation edge discontinuity shape | Hugh E. Stroupe, Gurtej S. Sandhu | 1997-09-09 |
| 5644166 | Sacrificial CVD germanium layer for formation of high aspect ratio submicron VLSI contacts | Jeffrey W. Honeycutt | 1997-07-01 |
| 5637518 | Method of making a field effect transistor having an elevated source and an elevated drain | Kirk D. Prall, Pai-Hung Pan | 1997-06-10 |
| 5533924 | Polishing apparatus, a polishing wafer carrier apparatus, a replacable component for a particular polishing apparatus and a process of polishing wafers | Hugh E. Stroupe, Gurtej S. Sandhu | 1996-07-09 |