Issued Patents All Time
Showing 1–25 of 40 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7432212 | Methods of processing a semiconductor substrate | Gurtej S. Sandhu | 2008-10-07 |
| 7226872 | Lightly doped drain MOS transistor | — | 2007-06-05 |
| 7115524 | Methods of processing a semiconductor substrate | Gurtej S. Sandhu | 2006-10-03 |
| 6894332 | Apparatus for reducing electrical shorts from the bit line to the cell plate | Kunal R. Parekh, Charles H. Dennison | 2005-05-17 |
| 6849537 | Method of suppressing void formation in a metal line | — | 2005-02-01 |
| 6838373 | Lightly doped drain MOS transistor | — | 2005-01-04 |
| 6808982 | Method of reducing electrical shorts from the bit line to the cell plate | Kunal R. Parekh, Charles H. Dennison | 2004-10-26 |
| 6777144 | Method for patterning a photoresist material for semiconductor component fabrication | Steven M. McDonald | 2004-08-17 |
| 6734071 | Methods of forming insulative material against conductive structures | Hassan Shahjamali, Daniel M. Smith | 2004-05-11 |
| 6723618 | Methods of forming field isolation structures | Russell L. Meyer, Stephen R. Porter | 2004-04-20 |
| 6709937 | Transistor structures | Hassan Shahjamali, Dani I Smith | 2004-03-23 |
| 6635396 | Method for providing an alignment diffraction grating for photolithographic alignment during semiconductor fabrication | Steven M. McDonald | 2003-10-21 |
| 6617689 | Metal line and method of suppressing void formation therein | — | 2003-09-09 |
| 6597042 | Contact with germanium layer | Sujit Sharan | 2003-07-22 |
| 6573013 | Method for providing an alignment diffraction grating for photolithographic alignment during semiconductor fabrication | Steven M. McDonald | 2003-06-03 |
| 6544871 | Method of suppressing void formation in a metal line | — | 2003-04-08 |
| 6524907 | Method of reducing electrical shorts from the bit line to the cell plate | Kunal R. Parekh, Charles H. Dennison | 2003-02-25 |
| 6501140 | Transistor structures | Hassan Shahjamali, Daniel M. Smith | 2002-12-31 |
| 6495406 | Method of forming lightly doped drain MOS transistor including forming spacers on gate electrode pattern before exposing gate insulator | — | 2002-12-17 |
| 6482572 | Method for providing an alignment diffraction grating for photolithographic alignment during semiconductor fabrication | Steven M. McDonald | 2002-11-19 |
| 6468859 | Method of reducing electrical shorts from the bit line to the cell plate | Kunal R. Parekh, Charles H. Dennison | 2002-10-22 |
| 6455212 | Method for providing an alignment diffraction grating for photolithographic alignment during semiconductor fabrication | Steven M. McDonald | 2002-09-24 |
| 6391746 | Gettering regions and methods of forming gettering regions within a semiconductor wafer | Fernando Gonzalez | 2002-05-21 |
| 6331482 | Method of VLSI contact, trench, and via filling using a germanium underlayer with metallization | Sujit Sharan | 2001-12-18 |
| 6309967 | Method of forming a contact | Sujit Sharan | 2001-10-30 |