JH

Jeffrey W. Honeycutt

Micron: 40 patents #475 of 6,345Top 8%
📍 Boise, ID: #269 of 3,546 inventorsTop 8%
🗺 Idaho: #362 of 8,810 inventorsTop 5%
Overall (All Time): #80,175 of 4,157,543Top 2%
40
Patents All Time

Issued Patents All Time

Showing 26–40 of 40 patents

Patent #TitleCo-InventorsDate
6239029 Sacrificial germanium layer for formation of a contact Sujit Sharan 2001-05-29
6229213 Germanium alloy electrical interconnect structure Sujit Sharan 2001-05-08
6114223 Gettering regions and methods of forming gettering regions within a semiconductor wafer Fernando Gonzalez 2000-09-05
6111325 Gettering regions and methods of forming gettering regions within a semiconductor wafer Fernando Gonzalez 2000-08-29
6093968 Germanium alloy contact to a silicon substrate Sujit Sharan 2000-07-25
6064098 Semiconductor processing methods of forming complementary metal oxide semiconductor memory and other circuitry, and memory and other circuitry Fernando Gonzalez 2000-05-16
6048778 Gettering regions and methods of forming gettering regions within a semiconductor wafer Fernando Gonzalez 2000-04-11
6040208 Angled ion implantation for selective doping Fernando Gonzalez, Fawad Ahmed 2000-03-21
5989946 Method of forming SRAM cells and pairs of field effect transistors 1999-11-23
5950079 Semiconductor processing methods of forming complementary metal oxide semiconductor memory and other circuitry Fernando Gonzalez 1999-09-07
5929507 Gettering regions and methods of forming gettering regions within a semiconductor wafer Fernando Gonzalez 1999-07-27
5773356 Gettering regions and methods of forming gettering regions within a semiconductor wafer Fernando Gonzalez 1998-06-30
5753956 Semiconductor processing methods of forming complementary metal oxide semiconductor memory and other circuitry, and memory and other circuitry Fernando Gonzalez 1998-05-19
5691217 Semiconductor processing method of forming a pair of field effect transistors having different thickness gate dielectric layers 1997-11-25
5644166 Sacrificial CVD germanium layer for formation of high aspect ratio submicron VLSI contacts Sujit Sharan 1997-07-01