Issued Patents All Time
Showing 26–50 of 78 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11782830 | Cache memory with randomized eviction | Amitava Majumdar, Sandeep Krishna Thirumala, Lingming Yang, Nevil N. Gajera | 2023-10-10 |
| 11778806 | Memory device having 2-transistor vertical memory cell and separate read and write gates | Eric Carman, Durai Vishak Nirmal Ramaswamy, Richard E. Fackenthal, Kamal M. Karda, Haitao Liu +2 more | 2023-10-03 |
| 11776907 | Memory device having 2-transistor vertical memory cell and a common plate | Kamal M. Karda, Haitao Liu, Durai Vishak Nirmal Ramaswamy | 2023-10-03 |
| 11775431 | Cache memory with randomized eviction | Amitava Majumdar, Sandeep Krishna Thirumala, Lingming Yang, Nevil N. Gajera | 2023-10-03 |
| 11735258 | Increase of a sense current in memory | Zhongyuan Lu, Robert J. Gleixner | 2023-08-22 |
| 11727983 | Single word line gain cell with complementary read write channel | Kamal M. Karda, Haitao Liu, Durai Vishak Nirmal Ramaswamy | 2023-08-15 |
| 11728005 | Bipolar read retry | Yen-Chun Lee, Nevil N. Gajera | 2023-08-15 |
| 11710528 | Data-based polarity write operations | Nevil N. Gajera, Hongmei Wang, Mingdong Cui | 2023-07-25 |
| 11694747 | Self-selecting memory cells configured to store more than one bit per memory cell | Lingming Yang, Xuan Anh Tran, Francesco Douglas Verna-Ketel, Jessica Chen, Nevil N. Gajera +1 more | 2023-07-04 |
| 11688450 | Memory device having 2-transistor vertical memory cell and shield structures | Kamal M. Karda, Haitao Liu, Durai Vishak Nirmal Ramaswamy, Alessandro Calderoni, Richard E. Fackenthal +1 more | 2023-06-27 |
| 11665880 | Memory device having 2-transistor vertical memory cell and a common plate | Kamal M. Karda, Haitao Liu, Durai Vishak Nirmal Ramaswamy | 2023-05-30 |
| 11664073 | Adaptively programming memory cells in different modes to optimize performance | Fabio Pellizzer, Nevil N. Gajera | 2023-05-30 |
| 11664074 | Programming intermediate state to store data in self-selecting memory cells | Nevil N. Gajera, Lingming Yang, Yen-Chun Lee, Jessica Chen, Francesco Douglas Verna-Ketel | 2023-05-30 |
| 11653489 | Memory device having 2-transistor vertical memory cell and shield structures | Kamal M. Karda, Haitao Liu, Durai Vishak Nirmal Ramaswamy | 2023-05-16 |
| 11631453 | Vertical 3D single word line gain cell with shared read/write bit line | Kamal M. Karda, Haitao Liu, Durai Vishak Nirmal Ramaswamy | 2023-04-18 |
| 11616098 | Three-dimensional memory arrays, and methods of forming the same | Lingming Yang, Fabio Pellizzer, Nevil N. Gajera, Lei Wei | 2023-03-28 |
| 11616073 | Memory device having 2-transistor vertical memory cell and wrapped data line structure | Kamal M. Karda, Eric Carman, Durai Vishak Nirmal Ramaswamy, Richard E. Fackenthal, Haitao Liu | 2023-03-28 |
| 11615854 | Identify the programming mode of memory cells during reading of the memory cells | Fabio Pellizzer, Nevil N. Gajera | 2023-03-28 |
| 11568952 | Adjustable programming pulses for a multi-level cell | Xuan Anh Tran, Nevil N. Gajera, Amitava Majumdar | 2023-01-31 |
| 11545194 | Dynamic read voltage techniques | Nevil N. Gajera, Jessica Chen, Lingming Yang | 2023-01-03 |
| 11545216 | Mitigation of voltage threshold drift associated with power down condition of non-volatile memory device | Fabio Pellizzer, Jessica Chen, Nevil N. Gajera | 2023-01-03 |
| 11538513 | Memory element for weight update in a neural network | Fabio Pellizzer | 2022-12-27 |
| 11532347 | Performing refresh operations of non-volatile memory to mitigate read disturb | Lingming Yang, Nevil N. Gajera, John Christopher Sancon | 2022-12-20 |
| 11527287 | Drift aware read operations | Nevil N. Gajera, Lingming Yang, John F. Schreck | 2022-12-13 |
| 11514983 | Identify the programming mode of memory cells based on cell statistics obtained during reading of the memory cells | Fabio Pellizzer, Nevil N. Gajera | 2022-11-29 |