Issued Patents All Time
Showing 76–100 of 120 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5933725 | Word line resistance reduction method and design for high density memory with relaxed metal pitch | Chih-Yuan Lu | 1999-08-03 |
| 5920221 | RC delay circuit for integrated circuits | Chiun-Chi Shen, Yen-Tai Lin, Jiang-Hong Ho, Jack-Lian Kuo | 1999-07-06 |
| 5896344 | Local word line decoder for memory with 2 1/2 MOS devices | Yen-Tai Lin | 1999-04-20 |
| 5867433 | Semiconductor memory with a novel column decoder for selecting a redundant array | Chiun-Chi Shen, Yen-Tai Lin, Jiang-Hong Ho, Jack-Lian Kuo | 1999-02-02 |
| 5867445 | Local word line decoder for memory with 2 MOS devices | Yen-Tai Lin | 1999-02-02 |
| 5821142 | Method for forming a capacitor with a multiple pillar structure | Janmye Sung, Chih-Yuan Lu | 1998-10-13 |
| 5792680 | Method of forming a low cost DRAM cell with self aligned twin tub CMOS devices and a pillar shaped capacitor | Janmye Sung, Chih-Yuan Lu | 1998-08-11 |
| 5786709 | Integrated circuit output driver incorporating power distribution noise suppression circuitry | Yen-Tai Lin, Chiun-Chi Shen, Jiang-Hong Ho, Jack-Lian Kuo | 1998-07-28 |
| 5739564 | Semiconductor device having a static-random-access memory cell | Yasunobu Kosa, Thomas F. McNelly, Frank K. Baker, Jr. | 1998-04-14 |
| 5616941 | Electrically programmable read-only memory cell | Scott S. Roth | 1997-04-01 |
| 5578856 | BicMOS device having a bipolar transistor and a MOS triggering transistor | Ravi Subrahmanyan | 1996-11-26 |
| 5543339 | Process for forming an electrically programmable read-only memory cell | Scott S. Roth | 1996-08-06 |
| 5536674 | Process for forming a static-random-access memory cell | Yasunobu Kosa, Thomas F. McNelly, Frank K. Baker, Jr. | 1996-07-16 |
| 5496756 | Method for forming a nonvolatile memory device | Umesh Sharma, Jim Hayden | 1996-03-05 |
| 5488579 | Three-dimensionally integrated nonvolatile SRAM cell and process | Umesh Sharma, Jim Hayden | 1996-01-30 |
| 5459083 | Method for making BIMOS device having a bipolar transistor and a MOS triggering transistor | Ravi Subrahmanyan | 1995-10-17 |
| 5445107 | Semiconductor device and method of formation | Scott S. Roth | 1995-08-29 |
| 5432731 | Ferroelectric memory cell and method of sensing and writing the polarization state thereof | Papu D. Maniar | 1995-07-11 |
| 5416736 | Vertical field-effect transistor and a semiconductor memory cell having the transistor | Yasunobu Kosa | 1995-05-16 |
| 5408130 | Interconnection structure for conductive layers | Michael P. Woo, James D. Hayden, Richard D. Sivan, Bich-Yen Nguyen | 1995-04-18 |
| 5374573 | Method of forming a self-aligned thin film transistor | Kent J. Cooper, Scott S. Roth, James D. Hayden | 1994-12-20 |
| 5364810 | Methods of forming a vertical field-effect transistor and a semiconductor memory cell | Yasunobu Kosa | 1994-11-15 |
| 5308997 | Self-aligned thin film transistor | Kent J. Cooper, Scott S. Roth, James D. Hayden | 1994-05-03 |
| 5286674 | Method for forming a via structure and semiconductor device having the same | Scott S. Roth | 1994-02-15 |
| 5272117 | Method for planarizing a layer of material | Scott S. Roth, Wayne J. Ray | 1993-12-21 |