Issued Patents All Time
Showing 51–75 of 120 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6888769 | Method and circuit for reducing DRAM refresh power by reducing access transistor sub threshold leakage | — | 2005-05-03 |
| 6856530 | System and method to avoid voltage read errors in open digit line array dynamic random access memories | — | 2005-02-15 |
| 6836427 | System and method to counteract voltage disturbances in open digitline array dynamic random access memory systems | Huy T. Vo, Charles L. Ingalls | 2004-12-28 |
| 6812799 | Synchronous mirror delay (SMD) circuit and method including a ring oscillator for timing coarse and fine delay intervals | — | 2004-11-02 |
| 6806137 | Trench buried bit line memory devices and methods thereof | Luan C. Tran, Mark Durcan | 2004-10-19 |
| 6803826 | Delay-locked loop circuit and method using a ring oscillator and counter-based delay | Tyler Gomm, Frank Alejano | 2004-10-12 |
| 6759911 | Delay-locked loop circuit and method using a ring oscillator and counter-based delay | Tyler Gomm, Frank Alejano | 2004-07-06 |
| 6754131 | Word line driver for negative voltage | Tae H. Kim, Charles L. Ingalls | 2004-06-22 |
| 6738301 | Method and system for accelerating coupling of digital signals | — | 2004-05-18 |
| 6734482 | Trench buried bit line memory devices | Luan C. Tran, Mark Durcan | 2004-05-11 |
| 6735103 | System and method to avoid voltage read errors in open digit line array dynamic random access memories | — | 2004-05-11 |
| 6727740 | Synchronous mirror delay (SMD) circuit and method including a ring oscillator for timing coarse and fine delay intervals | — | 2004-04-27 |
| 6621316 | Synchronous mirror delay (SMD) circuit and method including a counter and reduced size bi-directional delay line | — | 2003-09-16 |
| 6408264 | Switch level simulation with cross-coupled devices | Jason Su, Lidong Chen | 2002-06-18 |
| 6335633 | Adjustable, full CMOS input buffer for TTL, CMOS, or low swing input protocols | — | 2002-01-01 |
| 6327215 | Local bit switch decode circuit and method | Luigi Ternullo, Jr. | 2001-12-04 |
| 6320417 | Multiple-bit, current mode data bus | Ena Ku | 2001-11-20 |
| 6300795 | Multiple-bit, current mode data bus | Ena Ku | 2001-10-09 |
| 6275067 | Multiple-bit, current mode data bus | Ena Ku | 2001-08-14 |
| 6184714 | Multiple-bit, current mode data bus | Ena Ku | 2001-02-06 |
| 6166582 | Method and apparatus of an output buffer for controlling the ground bounce of a semiconductor device | Jiunn-Chin Tseng | 2000-12-26 |
| 6091264 | Schmitt trigger input stage | Yen-Tai Lin, Yu-Ming Hsu | 2000-07-18 |
| 6071774 | Method for forming a capacitor with a multiple pillar structure | Jan-Mye Sung, Chih-Yuan Lu | 2000-06-06 |
| 6057573 | Design for high density memory with relaxed metal pitch | Chih-Yuan Lu | 2000-05-02 |
| 6023174 | Adjustable, full CMOS input buffer for TTL, CMOS, or low swing input protocols | — | 2000-02-08 |