Issued Patents All Time
Showing 26–50 of 120 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7826293 | Devices and methods for a threshold voltage difference compensated sense amplifier | Tae H. Kim | 2010-11-02 |
| 7626877 | Low voltage sense amplifier and sensing method | Tae H. Kim, Charles L. Ingalls, David L. Pinney | 2009-12-01 |
| 7613024 | Local digit line architecture and method for memory devices having multi-bit or low capacitance memory cells | H. Montgomery Manning | 2009-11-03 |
| 7535282 | Dynamic well bias controlled by Vt detector | Tae H. Kim, Charles L. Ingalls, David L. Pinney | 2009-05-19 |
| 7512025 | Open digit line array architecture for a memory array | Sei Seung Yoon, Charles L. Ingalls, David L. Pinney | 2009-03-31 |
| 7505341 | Low voltage sense amplifier and sensing method | Tae H. Kim, Charles L. Ingalls, David L. Pinney | 2009-03-17 |
| 7460430 | Memory devices having reduced coupling noise between wordlines | Tae H. Kim, Charles L. Ingalls, Jeremy J. Gum | 2008-12-02 |
| 7440344 | Level shifter for low voltage operation | Tae H. Kim, Michael V. Cordoba | 2008-10-21 |
| 7417916 | Methods of reducing coupling noise between wordlines | Tae H. Kim, Charles L. Ingalls, Jeremy J. Gum | 2008-08-26 |
| 7365384 | Trench buried bit line memory devices and methods thereof | Luan C. Tran, Mark Durcan | 2008-04-29 |
| 7354812 | Multiple-depth STI trenches in integrated circuit fabrication | Shubneesh Batra, Gurtej S. Sandhu, Xianfeng Zhou, Chih-Chen Cho | 2008-04-08 |
| 7345937 | Open digit line array architecture for a memory array | Sei Seung Yoon, Charles L. Ingalls, David L. Pinney | 2008-03-18 |
| 7310257 | Local digit line architecture and method for memory devices having multi-bit or low capacitance memory cells | H. Montgomery Manning | 2007-12-18 |
| 7277310 | Open digit line array architecture for a memory array | Sei Seung Yoon, Charles L. Ingalls, David L. Pinney | 2007-10-02 |
| 7254074 | Open digit line array architecture for a memory array | Sei Seung Yoon, Charles L. Ingalls, David L. Pinney | 2007-08-07 |
| 7200053 | Level shifter for low voltage operation | Tae H. Kim, Michael V. Cordoba | 2007-04-03 |
| 7193914 | Open digit line array architecture for a memory array | Sei Seung Yoon, Charles L. Ingalls, David L. Pinney | 2007-03-20 |
| 7170124 | Trench buried bit line memory devices and methods thereof | Luan C. Tran, Mark Durcan | 2007-01-30 |
| 7110319 | Memory devices having reduced coupling noise between wordlines | Tae H. Kim, Charles L. Ingalls, Jeremy J. Gum | 2006-09-19 |
| 7034572 | Voltage level shifting circuit and method | Tae H. Kim | 2006-04-25 |
| 7023751 | Method and circuit for reducing DRAM refresh power by reducing access transistor sub threshold leakage | — | 2006-04-04 |
| 6934208 | Apparatus and method for a current limiting bleeder device shared by columns of different memory arrays | J. Wayne Thompson, George B. Raad | 2005-08-23 |
| 6925019 | Method and system for accelerating coupling of digital signals | — | 2005-08-02 |
| 6924686 | Synchronous mirror delay (SMD) circuit and method including a counter and reduced size bi-directional delay line | — | 2005-08-02 |
| 6901023 | Word line driver for negative voltage | Tae H. Kim, Charles L. Ingalls | 2005-05-31 |