Issued Patents All Time
Showing 51–62 of 62 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10256249 | Integrated structures | Justin B. Dorhout, Kunal R. Parekh, Martin C. Roberts, Yushi Hu | 2019-04-09 |
| 10229923 | Integrated assemblies and methods of forming integrated assemblies | Justin B. Dorhout, Kunal R. Parekh, Martin C. Roberts, Mohd Kamran Akhtar, Chet E. Carter | 2019-03-12 |
| 10224336 | Integrated circuitry and 3D memory | — | 2019-03-05 |
| 10083981 | Memory arrays, and methods of forming memory arrays | Richard J. Hill, Christopher J. Larsen, Woohee Kim, Justin B. Dorhout, Brett D. Lowe +3 more | 2018-09-25 |
| 10038008 | Integrated structures and NAND memory arrays | John D. Hopkins | 2018-07-31 |
| 9985040 | Integrated circuitry and 3D memory | — | 2018-05-29 |
| 9857989 | Solid state memory component | Jun Zhao, Gowrisankar Damarla, Gordon A. Haller, Sri Sai Sivakumar Vegunta, John B. Matovu +2 more | 2018-01-02 |
| 9853037 | Integrated assemblies | Justin B. Dorhout, Kunal R. Parekh, Martin C. Roberts, Mohd Kamran Akhtar, Chet E. Carter | 2017-12-26 |
| 9741732 | Integrated structures | Justin B. Dorhout, Kunal R. Parekh, Martin C. Roberts, Yushi Hu | 2017-08-22 |
| 9153455 | Methods of forming semiconductor device structures, memory cells, and arrays | Christopher J. Larsen, Kunal Shrotri | 2015-10-06 |
| 8563435 | Method of reducing damage to an electron beam inspected semiconductor substrate, and methods of inspecting a semiconductor substrate | Paul A. Morgan, Shawn D. Lyonsmith, Curtis R. Olson | 2013-10-22 |
| 8334209 | Method of reducing electron beam damage on post W-CMP wafers | Paul A. Morgan, Shawn D. Lyonsmith, Curtis R. Olson | 2012-12-18 |