Issued Patents All Time
Showing 26–50 of 69 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8359479 | High performance arithmetic logic unit (ALU) for cryptographic applications with built-in countermeasures against side channel attacks | Mikhail I. Grinchuk, Lav D. Ivanovic, Paul G. Filseth | 2013-01-22 |
| 8302083 | Architecture and implementation method of programmable arithmetic controller for cryptographic applications | Mikhail I. Grinchuk, Lav D. Ivanovic, Alexei V. Galatenko | 2012-10-30 |
| 8160242 | Efficient implementation of arithmetical secure hash techniques | Mikhail I. Grinchuk, Lay D. Ivanovic, Andrej A. Zolotykh, Alexei V. Galatenko | 2012-04-17 |
| 8156391 | Data controlling in the MBIST chain architecture | Alexandre Andreev, Mikhail I. Grinchuk | 2012-04-10 |
| 8132075 | Memory mapping for parallel turbo decoding | Alexander E. Andreev, Ranko Scepanovic | 2012-03-06 |
| 8063659 | Low depth programmable priority encoders | Mikhail I. Grinchuk, Sergei B. Gashkov, Lav D. Ivanovic | 2011-11-22 |
| 8046643 | Transport subsystem for an MBIST chain architecture | Alexandre Andreev, Mikhail I. Grinchuk | 2011-10-25 |
| 8023644 | Multimode block cipher architectures | Mikhail I. Grinchuk, Lav D. Ivanovic, Paul G. Filseth, Anton I. Sabev | 2011-09-20 |
| 7961872 | Flexible hardware architecture for ECC/HECC based cryptography | Mlkhail I. Grinchuk, Paul G. Filseth, Lav D. Ivanovic | 2011-06-14 |
| 7949909 | Address controlling in the MBIST chain architecture | Alexandre Andreev, Mikhail I. Grinchuk | 2011-05-24 |
| 7890565 | Efficient hardware implementation of tweakable block cipher | Mikhail I. Grinchuk | 2011-02-15 |
| 7882406 | Built in test controller with a downloadable testing program | Alexander E. Andreev | 2011-02-01 |
| 7856577 | Command language for memory testing | Alexander E. Andreev, Ranko Scepanovic | 2010-12-21 |
| 7839164 | Low depth programmable priority encoders | Mikhail I. Grinchuk, Sergei B. Gashkov, Lav D. Ivanovic | 2010-11-23 |
| 7818703 | Density driven layout for RRAM configuration module | Alexander E. Andreev, Ivan Pavisic | 2010-10-19 |
| 7788563 | Generation of test sequences during memory built-in self testing of multiple memories | Alexandre Andreev, Ranko Scepanovic | 2010-08-31 |
| 7548844 | Sequential tester for longest prefix search engines | Alexander E. Andreev | 2009-06-16 |
| 7430694 | Memory BISR architecture for a slice | Alexander E. Andreev, Sergey Gribok | 2008-09-30 |
| 7415686 | Memory timing model with back-annotating | Alexander E. Andreev, Ranko Scepanovic | 2008-08-19 |
| 7328382 | Memory BISR controller architecture | Alexander E. Andreev, Sergey Gribok | 2008-02-05 |
| 7308633 | Master controller architecture | Alexandre Andreev, Sergey Gribok | 2007-12-11 |
| 7305593 | Memory mapping for parallel turbo decoding | Alexander E. Andreev, Ranko Scepanovic | 2007-12-04 |
| 7283385 | RRAM communication system | Alexander E. Andreev, Sergey Gribok | 2007-10-16 |
| 7246337 | Density driven layout for RRAM configuration module | Alexander E. Andreev, Ivan Pavisic | 2007-07-17 |
| 7231383 | Search engine for large-width data | Alexander E. Andreev, Ranko Scepanovic | 2007-06-12 |