Issued Patents All Time
Showing 51–69 of 69 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7219321 | Process and apparatus for memory mapping | Andrey Nikitin, Alexander E. Andreev | 2007-05-15 |
| 7216278 | Method and BIST architecture for fast memory testing in platform-based integrated circuit | Alexander E. Andreev, Ranko Scepanovic | 2007-05-08 |
| 7200785 | Sequential tester for longest prefix search engines | Alexander E. Andreev | 2007-04-03 |
| 7194717 | Compact custom layout for RRAM column controller | Alexander E. Andreev, Ivan Pavisic | 2007-03-20 |
| 7181563 | FIFO memory with single port memory modules for allowing simultaneous read and write operations | Alexander E. Andreev, Ranko Scepanovic | 2007-02-20 |
| 7082561 | Built-in functional tester for search engines | Alexander E. Andreev, Nikola Radovanovic | 2006-07-25 |
| 7072922 | Integrated circuit and process for identifying minimum or maximum input value among plural inputs | Alexander E. Andreev, Igor Vikhliantsev | 2006-07-04 |
| 7062726 | Method for generating tech-library for logic function | Alexander E. Andreev, Igor Vikhliantsev | 2006-06-13 |
| 7020865 | Process for designing comparators and adders of small depth | Mikhail I. Grinchuk | 2006-03-28 |
| 6886088 | Memory that allows simultaneous read requests | Egor A. Andreev, Ranko Scepanovic, Alexander E. Andreev | 2005-04-26 |
| 6662287 | Fast free memory address controller | Alexander E. Andreev, Ranko Scepanovic | 2003-12-09 |
| 6587990 | Method and apparatus for formula area and delay minimization | Alexander E. Andreev, Ranko Scepanovic | 2003-07-01 |
| 6536016 | Method and apparatus for locating constants in combinational circuits | Alexander E. Andreev, Ranko Scepanovic | 2003-03-18 |
| 6530063 | Method and apparatus for detecting equivalent and anti-equivalent pins | Alexander E. Andreev, Ranko Scepanovic | 2003-03-04 |
| 6519746 | Method and apparatus for minimization of net delay by optimal buffer insertion | Alexander E. Andreev, Ranko Scepanovic | 2003-02-11 |
| 6507939 | Net delay optimization with ramptime violation removal | Alexander E. Andreev, Igor Vikhliantsev | 2003-01-14 |
| 6505336 | Channel router with buffer insertion | Alexander E. Andreev, Pedja Raspopovic | 2003-01-07 |
| 6453453 | Process for solving assignment problems in integrated circuit designs with unimodal object penalty functions and linearly ordered set of boxes | Alexander E. Andreev, Pedja Raspopovic | 2002-09-17 |
| 6292924 | Modifying timing graph to avoid given set of paths | Ivan Pavisic, Alexander E. Andreev, Ranko Scepanovic | 2001-09-18 |