Issued Patents All Time
Showing 1–22 of 22 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12032892 | Semiconductor layout context around a point of interest | Mohamed Alimam Mohamed Selim, Mohamed Bahnas, Hazem Hegazy, Ahmed Hamed Fathi Hamed | 2024-07-09 |
| 10552565 | Simultaneous multi-layer fill generation | Eugene Anikin, Fedor G. Pikus, Laurence W. Grodd, John W. Stedman | 2020-02-04 |
| 9652574 | Simultaneous multi-layer fill generation | Eugene Anikin, Fedor G. Pikus, Laurence W. Grodd, John W. Stedman | 2017-05-16 |
| 8612919 | Model-based design verification | Fedor G. Pikus | 2013-12-17 |
| 7930655 | Yield profile manipulator | ChandraSekhar Desu, Nima A. Behkami, Bruce Whitefield, David J. Sturtevant | 2011-04-19 |
| 7725849 | Feature failure correlation | Bernd Koenemann | 2010-05-25 |
| 7653523 | Method for calculating high-resolution wafer parameter profiles | Bruce Whitefield | 2010-01-26 |
| 7460211 | Apparatus for wafer patterning to reduce edge exclusion zone | Bruce Whitefield | 2008-12-02 |
| 7454387 | Method of isolating sources of variance in parametric data | Thaddeus T. Shannon, III, James McNames | 2008-11-18 |
| 7395522 | Yield profile manipulator | ChandraSekhar Desu, Nima A. Behkami, Bruce Whitefield, David J. Sturtevant | 2008-07-01 |
| 7390680 | Method to selectively identify reliability risk die based on characteristics of local regions on the wafer | Ramon Gonzales, Kevin Cota, Manu Rehani | 2008-06-24 |
| 7174281 | Method for analyzing manufacturing data | — | 2007-02-06 |
| 7137098 | Pattern component analysis and manipulation | Bruce Whitefield, David Ray Turner, James McNames | 2006-11-14 |
| 7062415 | Parametric outlier detection | Bruce Whitefield, David Ray Turner, James McNames | 2006-06-13 |
| 7039556 | Substrate profile analysis | Bruce Whitefield | 2006-05-02 |
| 6980917 | Optimization of die yield in a silicon wafer “sweet spot” | Mark Ward, Larry Kelley | 2005-12-27 |
| 6880140 | Method to selectively identify reliability risk die based on characteristics of local regions on the wafer | Ramon Gonzales, Kevin Cota, Manu Rehani | 2005-04-12 |
| 6807655 | Adaptive off tester screening method based on intrinsic die parametric measurements | Manu Rehani, Kevin Cota, Robert Madge | 2004-10-19 |
| 6658361 | Heaviest only fail potential | Manu Rehani, Ramkumar Vaidyanathan | 2003-12-02 |
| 5937324 | Method for forming a line-on-line multi-level metal interconnect structure for use in integrated circuits | Rickey S. Brownson, Michael R. Cherniawski | 1999-08-10 |
| 5798568 | Semiconductor component with multi-level interconnect system and method of manufacture | Rickey S. Brownson, Michael R. Cherniawski | 1998-08-25 |
| 5666063 | Method and apparatus for testing an integrated circuit | Whitson G. Waldo, III | 1997-09-09 |