MM

Mie Matsuo

KT Kabushiki Kaisha Toshiba: 47 patents #379 of 21,451Top 2%
Kioxia: 8 patents #149 of 1,813Top 9%
Toshiba Memory: 2 patents #853 of 1,971Top 45%
JS Jsr: 1 patents #649 of 1,137Top 60%
NT Nuflare Technology: 1 patents #192 of 298Top 65%
TS Toshiba Electronic Devices & Storage: 1 patents #470 of 900Top 55%
📍 Yokkaichi, JP: #40 of 2,072 inventorsTop 2%
Overall (All Time): #41,503 of 4,157,543Top 1%
58
Patents All Time

Issued Patents All Time

Showing 51–58 of 58 patents

Patent #TitleCo-InventorsDate
6709966 Semiconductor device, its manufacturing process, position matching mark, pattern forming method and pattern forming device Yoshimi Hisatsune, Keiichi Sasaki, Hiroshi Ikegami, Nobuo Hayasaka, Katsuya Okumura 2004-03-23
6614106 Stacked circuit device and method for evaluating an integrated circuit substrate using the stacked circuit device Nobuo Hayasaka 2003-09-02
6504227 Passive semiconductor device mounted as daughter chip on active semiconductor device Nobuo Hayasaka, Noriaki Matsunaga, Katsuya Okumura 2003-01-07
5775980 Polishing method and polishing apparatus Yasutaka Sasaki, Rempei Nakata, Junichi Wada, Nobuo Hayasaka, Hiroyuki Yano +1 more 1998-07-07
5731634 Semiconductor device having a metal film formed in a groove in an insulating film Haruo Okano, Nobuo Hayasaka, Kyoichi Suguro, Hideshi Miyajima, Jun Wada 1998-03-24
5607718 Polishing method and polishing apparatus Yasutaka Sasaki, Rempei Nakata, Junichi Wada, Nobuo Hayasaka, Hiroyuki Yano +1 more 1997-03-04
5561082 Method for forming an electrode and/or wiring layer by reducing copper oxide or silver oxide Haruo Okano, Nobuo Hayasaka, Kyoichi Suguro, Hideshi Miyajima, Jun Wada 1996-10-01
5424246 Method of manufacturing semiconductor metal wiring layer by reduction of metal oxide Haruo Okano, Nobuo Hayasaka, Kyoichi Suguro, Hideshi Miyajima, Jun Wada 1995-06-13