Issued Patents All Time
Showing 25 most recent of 240 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12308074 | Enhanced gradient seeding scheme during a program operation in a memory sub-system | Vinh Diep, Ching-Huang Lu | 2025-05-20 |
| 12300322 | Selective increase and decrease to pass voltages for programming a memory device | Vinh Diep, Jeffrey Ming-Hung Tsai, Ching-Huang Lu | 2025-05-13 |
| 12217801 | Bias voltage schemes during pre-programming and programming phases | Vinh Diep, Ching-Huang Lu | 2025-02-04 |
| 12200928 | Memory device having memory cell strings and separate read and write control gates | Haitao Liu, Kamal M. Karda, Albert Fayrushin | 2025-01-14 |
| 11967387 | Detrapping electrons to prevent quick charge loss during program verify operations in a memory device | Ching-Huang Lu, Vinh Diep, Zhengyi Zhang | 2024-04-23 |
| 11956954 | Electronic devices comprising reduced charge confinement regions in storage nodes of pillars and related methods | Yifen Liu, Yan Song, Albert Fayrushin, Naiming Liu, George Matamis | 2024-04-09 |
| 11901010 | Enhanced gradient seeding scheme during a program operation in a memory sub-system | Vinh Diep, Ching-Huang Lu | 2024-02-13 |
| 11791003 | Distributed compaction of logical states to reduce program time | Kalyan C. Kavalipurapu, George Matamis, Chang Hua Siau | 2023-10-17 |
| 11749359 | Short program verify recovery with reduced programming disturbance in a memory sub-system | Hong-Yan Chen | 2023-09-05 |
| 11688474 | Dual verify for quick charge loss reduction in memory cells | Violante Moschiano | 2023-06-27 |
| 11688471 | Short program verify recovery with reduced programming disturbance in a memory sub-system | Hong-Yan Chen | 2023-06-27 |
| 11688476 | Apparatus and methods for seeding operations concurrently with data line set operations | Jun Xu | 2023-06-27 |
| 11670372 | Pre-boosting scheme during a program operation in a memory sub-system | Hong-Yan Chen | 2023-06-06 |
| 11508449 | Detrapping electrons to prevent quick charge loss during program verify operations in a memory device | Ching-Huang Lu, Vinh Diep, Zhengyi Zhang | 2022-11-22 |
| 11488677 | Distributed compaction of logical states to reduce program time | Kalyan C. Kavalipurapu, George Matamis, Chang Hua Siau | 2022-11-01 |
| 11380709 | Three dimensional ferroelectric memory | James Kai, Christopher J. Petti | 2022-07-05 |
| 11282582 | Short program verify recovery with reduced programming disturbance in a memory sub-system | Hong-Yan Chen | 2022-03-22 |
| 11238946 | Apparatus and methods for seeding operations concurrently with data line set operations | Jun Xu | 2022-02-01 |
| 11183245 | Pre-boosting scheme during a program operation in a memory sub-system | Hong-Yan Chen | 2021-11-23 |
| 11037640 | Multi-pass programming process for memory device which omits verify test in first program pass | Ashish Baraskar, Ching-Huang Lu, Vinh Diep | 2021-06-15 |
| 10998331 | Three-dimensional inverse flat NAND memory device containing partially discrete charge storage elements and methods of making the same | Fei Zhou, Raghuveer S. Makala | 2021-05-04 |
| 10854304 | Apparatus and methods for seeding operations concurrently with data line set operations | Jun Xu | 2020-12-01 |
| 10811109 | Multi-pass programming process for memory device which omits verify test in first program pass | Ashish Baraskar, Ching-Huang Lu, Vinh Diep | 2020-10-20 |
| 10755788 | Impedance mismatch mitigation scheme that applies asymmetric voltage pulses to compensate for asymmetries from applying symmetric voltage pulses | Peter Rabkin, Kwang Ho Kim, Masaaki Higashitani | 2020-08-25 |
| 10748627 | Reducing neighbor word line interference in a two-tier memory device by modifying word line programming order | Hong-Yan Chen, Zhengyi Zhang | 2020-08-18 |