Issued Patents All Time
Showing 1–25 of 29 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12243584 | In-memory compute array with integrated bias elements | Anuj Grover, Nitin Chawla | 2025-03-04 |
| 11889675 | Dual port memory cell with improved access resistance | Tushar Sharma, Shishir Kumar | 2024-01-30 |
| 11829730 | Elements for in-memory compute | Nitin Chawla, Anuj Grover, Giuseppe Desoli | 2023-11-28 |
| 11798615 | High density array, in memory computing | Anuj Grover | 2023-10-24 |
| 11776650 | Memory calibration device, system and method | Anuj Grover | 2023-10-03 |
| 11749343 | Memory management device, system and method | Nitin Chawla, Anuj Grover | 2023-09-05 |
| 11742045 | Testing of comparators within a memory safety logic circuit using a fault enable generation circuit within the memory | Rohit Bhasin, Shishir Kumar, Deepak Kumar Bihani | 2023-08-29 |
| 11605424 | In-memory compute array with integrated bias elements | Anuj Grover, Nitin Chawla | 2023-03-14 |
| 11532633 | Dual port memory cell with improved access resistance | Tushar Sharma, Shishir Kumar | 2022-12-20 |
| 11474788 | Elements for in-memory compute | Nitin Chawla, Anuj Grover, Giuseppe Desoli | 2022-10-18 |
| 11398289 | Memory calibration device, system and method | Anuj Grover | 2022-07-26 |
| 11393532 | Circuit and method for at speed detection of a word line fault condition in a memory circuit | Tanuj KUMAR, Shishir Kumar | 2022-07-19 |
| 11335397 | High-density array, in memory computing | Anuj Grover | 2022-05-17 |
| 11257543 | Memory management device, system and method | Nitin Chawla, Anuj Grover | 2022-02-22 |
| 11152376 | Dual port memory cell with improved access resistance | Tushar Sharma, Shishir Kumar | 2021-10-19 |
| 11094376 | In-memory compute array with integrated bias elements | Anuj Grover, Nitin Chawla | 2021-08-17 |
| 10998077 | Testing of comparators within a memory safety logic circuit using a fault enable generation circuit within the memory | Rohit Bhasin, Shishir Kumar, Deepak Kumar Bihani | 2021-05-04 |
| 10706915 | Method and circuit for adaptive read-write operation in self-timed memory | Abhishek Pathak, Shishir Kumar | 2020-07-07 |
| 10637447 | Low voltage, master-slave flip-flop | Alok Tripathi, Amit Verma, Anuj Grover, Deepak Kumar Bihani, Tanuj Agrawal | 2020-04-28 |
| 10283191 | Method and circuit for adaptive read-write operation in self-timed memory | Abhishek Pathak, Shishir Kumar | 2019-05-07 |
| 10277207 | Low voltage, master-slave flip-flop | Alok Tripathi, Amit Verma, Anuj Grover, Deepak Kumar Bihani, Tanuj Agrawal | 2019-04-30 |
| 9590602 | System and method for a pulse generator | Shishir Kumar | 2017-03-07 |
| 8458545 | Method and apparatus for testing of a memory with redundancy elements | Harsh Rawat, Swapnil Bahl, Amit Chhabra, Nitin Jain, Jatin Fultaria | 2013-06-04 |
| 7791970 | Biased sensing module | Nasim Ahmad | 2010-09-07 |
| 6937971 | System and method for determining the desired decoupling components for a power distribution system having a voltage regulator module | Larry D. Smith, Raymond E. Anderson | 2005-08-30 |