| 8127192 |
Predicting lwarx and stwcx instructions in test pattern generation and simulation for processor design verification/validation in interrupt mode |
Sampan Arora, Divya S. Anvekar, Manoj Dusanapudi, Shakti Kapoor, Bhavani Shringari Nanjundiah |
2012-02-28 |
| 8099559 |
System and method for generating fast instruction and data interrupts for processor design verification and validation |
Shubhodeep Roy Choudhury, Manoj Dusanapudi, Shakti Kapoor, Rahul Sharad Moharil |
2012-01-17 |
| 8019566 |
System and method for efficiently testing cache congruence classes during processor design verification and validation |
Vinod Bussa, Shubhodeep Roy Choudhury, Manoj Dusanapudi, Shakti Kapoor, Batchu Naga Venkata Satyanarayana |
2011-09-13 |
| 8006221 |
System and method for testing multiple processor modes for processor design verification and validation |
Sampan Arora, Shubhodeep Roy Choudhury, Manoj Dusanapudi, Shakti Kapoor, Sai Rupak Mohanan |
2011-08-23 |
| 7992059 |
System and method for testing a large memory area during processor design verification and validation |
Divya S. Anvekar, Shubhodeep Roy Choudhury, Manoj Dusanapudi, Shakti Kapoor |
2011-08-02 |
| 7966521 |
Light weight and high throughput test case generation methodology for testing cache/TLB intervention and diagnostics |
Vinod Bussa, Manoj Dusanapudi, Shakti Kapoor |
2011-06-21 |
| 7797650 |
System and method for testing SLB and TLB cells during processor design verification and validation |
Sandip Bag, Manoj Dusanapudi, Shakti Kapoor, Batchu Naga Venkata Satyanarayana |
2010-09-14 |
| 7752499 |
System and method for using resource pools and instruction pools for processor design verification and validation |
Shubhodeep Roy Choudhury, Manoj Dusanapudi, Shakti Kapoor, Rahul Sharad Moharil |
2010-07-06 |
| 7747908 |
System and method for creating different start cache and bus states using multiple test patterns for processor design verification and validation |
Shubhodeep Roy Choudhury, Manoj Dusanapudi, Shakti Kapoor, Chakrapani Rayadurgam, Batchu Naga Venkata Satyanarayana |
2010-06-29 |
| 7739570 |
System and method for increasing error checking performance by calculating CRC calculations after multiple test patterns for processor design verification and validation |
Sandip Bag, Shubhodeep Roy Choudhury, Manoj Dusanapudi, Shakti Kapoor, Rahul Sharad Moharil |
2010-06-15 |
| 7689886 |
System and method for predicting lwarx and stwcx instructions in test pattern generation and simulation for processor design verification and validation |
Sampan Arora, Divya S. Anvekar, Manoj Dusanapudi, Shakti Kapoor, Bhavani Shringari Nanjundiah |
2010-03-30 |
| 7669083 |
System and method for re-shuffling test case instruction orders for processor design verification and validation |
Sampan Arora, Sandip Bag, Vinod Bussa, Shubhodeep Roy Choudhury, Manoj Dusanapudi +3 more |
2010-02-23 |
| 7661023 |
System and method for verification of cache snoop logic and coherency between instruction & data caches for processor design verification and validation |
Sampan Arora, Shubhodeep Roy Choudhury, Manoj Dusanapudi, Shakti Kapoor, Chakrapani Rayadurgam |
2010-02-09 |
| 7647539 |
System and method of testing using test pattern re-execution in varying timing scenarios for processor design verification and validation |
Vinod Bussa, Manoj Dusanapudi, Shakti Kapoor, Rahul Sharad Moharil, Bhavani Shringari Nanjundiah |
2010-01-12 |
| 7584394 |
System and method for pseudo-random test pattern memory allocation for processor design verification and validation |
Shubhodeep Roy Choudhury, Sandip Bag, Manoj Dusanapudi, Shakti Kapoor, Bhavani Shringari Nanjundiah |
2009-09-01 |
